linux-headers: update from kvm/next (fff02bc0) · Commits · SUMMER2020 / students / proj-2021291

hw/display/virtio-gpu.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -146,14 +146,14 @@ static uint64_t virtio_gpu_get_features(VirtIODevice *vdev, uint64_t features,
		VirtIOGPU *g = VIRTIO_GPU(vdev);

		if (virtio_gpu_virgl_enabled(g->conf)) {
		features \|= (1 << VIRTIO_GPU_FEATURE_VIRGL);
		features \|= (1 << VIRTIO_GPU_F_VIRGL);
		}
		return features;
		}

		static void virtio_gpu_set_features(VirtIODevice *vdev, uint64_t features)
		{
		static const uint32_t virgl = (1 << VIRTIO_GPU_FEATURE_VIRGL);
		static const uint32_t virgl = (1 << VIRTIO_GPU_F_VIRGL);
		VirtIOGPU *g = VIRTIO_GPU(vdev);

		g->use_virgl_renderer = ((features & virgl) == virgl);

include/standard-headers/asm-x86/hyperv.h

+104 −0

Original line number	Diff line number	Diff line
		@@ -257,4 +257,108 @@ typedef struct _HV_REFERENCE_TSC_PAGE {
		int64_t tsc_offset;
		} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;

		/* Define the number of synthetic interrupt sources. */
		#define HV_SYNIC_SINT_COUNT (16)
		/* Define the expected SynIC version. */
		#define HV_SYNIC_VERSION_1 (0x1)

		#define HV_SYNIC_CONTROL_ENABLE (1ULL << 0)
		#define HV_SYNIC_SIMP_ENABLE (1ULL << 0)
		#define HV_SYNIC_SIEFP_ENABLE (1ULL << 0)
		#define HV_SYNIC_SINT_MASKED (1ULL << 16)
		#define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17)
		#define HV_SYNIC_SINT_VECTOR_MASK (0xFF)

		#define HV_SYNIC_STIMER_COUNT (4)

		/* Define synthetic interrupt controller message constants. */
		#define HV_MESSAGE_SIZE (256)
		#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240)
		#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30)

		/* Define hypervisor message types. */
		enum hv_message_type {
		HVMSG_NONE = 0x00000000,

		/* Memory access messages. */
		HVMSG_UNMAPPED_GPA = 0x80000000,
		HVMSG_GPA_INTERCEPT = 0x80000001,

		/* Timer notification messages. */
		HVMSG_TIMER_EXPIRED = 0x80000010,

		/* Error messages. */
		HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
		HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021,
		HVMSG_UNSUPPORTED_FEATURE = 0x80000022,

		/* Trace buffer complete messages. */
		HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040,

		/* Platform-specific processor intercept messages. */
		HVMSG_X64_IOPORT_INTERCEPT = 0x80010000,
		HVMSG_X64_MSR_INTERCEPT = 0x80010001,
		HVMSG_X64_CPUID_INTERCEPT = 0x80010002,
		HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003,
		HVMSG_X64_APIC_EOI = 0x80010004,
		HVMSG_X64_LEGACY_FP_ERROR = 0x80010005
		};

		/* Define synthetic interrupt controller message flags. */
		union hv_message_flags {
		uint8_t asu8;
		struct {
		uint8_t msg_pending:1;
		uint8_t reserved:7;
		};
		};

		/* Define port identifier type. */
		union hv_port_id {
		uint32_t asu32;
		struct {
		uint32_t id:24;
		uint32_t reserved:8;
		} u;
		};

		/* Define synthetic interrupt controller message header. */
		struct hv_message_header {
		uint32_t message_type;
		uint8_t payload_size;
		union hv_message_flags message_flags;
		uint8_t reserved[2];
		union {
		uint64_t sender;
		union hv_port_id port;
		};
		};

		/* Define synthetic interrupt controller message format. */
		struct hv_message {
		struct hv_message_header header;
		union {
		uint64_t payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
		} u;
		};

		/* Define the synthetic interrupt message page layout. */
		struct hv_message_page {
		struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
		};

		/* Define timer message payload structure. */
		struct hv_timer_message_payload {
		uint32_t timer_index;
		uint32_t reserved;
		uint64_t expiration_time; /* When the timer expired */
		uint64_t delivery_time; /* When the message was delivered */
		};

		#define HV_STIMER_ENABLE (1ULL << 0)
		#define HV_STIMER_PERIODIC (1ULL << 1)
		#define HV_STIMER_LAZY (1ULL << 2)
		#define HV_STIMER_AUTOENABLE (1ULL << 3)
		#define HV_STIMER_SINT(config) (uint8_t)(((config) >> 16) & 0x0F)

		#endif

include/standard-headers/linux/input-event-codes.h

0 → 100644

+805 −0

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include/standard-headers/linux/input.h

+66 −784

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include/standard-headers/linux/pci_regs.h

+42 −1

Original line number	Diff line number	Diff line
		@@ -216,7 +216,8 @@
		#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
		#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
		#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
		#define PCI_CAP_ID_MAX PCI_CAP_ID_AF
		#define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */
		#define PCI_CAP_ID_MAX PCI_CAP_ID_EA
		#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
		#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
		#define PCI_CAP_SIZEOF 4
		@@ -353,6 +354,46 @@
		#define PCI_AF_STATUS_TP 0x01
		#define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */

		/* PCI Enhanced Allocation registers */

		#define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */
		#define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */
		#define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */
		#define PCI_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */
		#define PCI_EA_ES 0x00000007 /* Entry Size */
		#define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */
		/* 0-5 map to BARs 0-5 respectively */
		#define PCI_EA_BEI_BAR0 0
		#define PCI_EA_BEI_BAR5 5
		#define PCI_EA_BEI_BRIDGE 6 /* Resource behind bridge */
		#define PCI_EA_BEI_ENI 7 /* Equivalent Not Indicated */
		#define PCI_EA_BEI_ROM 8 /* Expansion ROM */
		/* 9-14 map to VF BARs 0-5 respectively */
		#define PCI_EA_BEI_VF_BAR0 9
		#define PCI_EA_BEI_VF_BAR5 14
		#define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */
		#define PCI_EA_PP 0x0000ff00 /* Primary Properties */
		#define PCI_EA_SP 0x00ff0000 /* Secondary Properties */
		#define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */
		#define PCI_EA_P_MEM_PREFETCH 0x01 /* Prefetchable Memory */
		#define PCI_EA_P_IO 0x02 /* I/O Space */
		#define PCI_EA_P_VF_MEM_PREFETCH 0x03 /* VF Prefetchable Memory */
		#define PCI_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */
		#define PCI_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */
		#define PCI_EA_P_BRIDGE_MEM_PREFETCH 0x06 /* Bridge Prefetchable Memory */
		#define PCI_EA_P_BRIDGE_IO 0x07 /* Bridge I/O Space */
		/* 0x08-0xfc reserved */
		#define PCI_EA_P_MEM_RESERVED 0xfd /* Reserved Memory */
		#define PCI_EA_P_IO_RESERVED 0xfe /* Reserved I/O Space */
		#define PCI_EA_P_UNAVAILABLE 0xff /* Entry Unavailable */
		#define PCI_EA_WRITABLE 0x40000000 /* Writable: 1 = RW, 0 = HwInit */
		#define PCI_EA_ENABLE 0x80000000 /* Enable for this entry */
		#define PCI_EA_BASE 4 /* Base Address Offset */
		#define PCI_EA_MAX_OFFSET 8 /* MaxOffset (resource length) */
		/* bit 0 is reserved */
		#define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
		#define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */

		/* PCI-X registers (Type 0 (non-bridge) devices) */

		#define PCI_X_CMD 2 /* Modes & Features */