Commit ffebe899 authored by Stefan Weil's avatar Stefan Weil Committed by Peter Maydell
Browse files

disas/libvixl: Fix wrong format strings 



When the compiler is told to check the arguments of AppendToOutput,
it reports several errors of this kind:

error: format ‘%d’ expects argument of type ‘int’,
 but argument 3 has type ‘int64_t {aka long int}’ [-Werror=format]

Fix those bugs by using the correct format strings with PRId64, PRIx64.

Signed-off-by: default avatarStefan Weil <sw@weilnetz.de>
Message-id: 1403113751-19799-1-git-send-email-sw@weilnetz.de
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 1ce8be7e

disas/libvixl/a64/disasm-a64.cc

+10 −10
Original line number Diff line number Diff line
@@ -1369,7 +1369,7 @@ int Disassembler::SubstituteImmediateField(Instruction* instr, 
        VIXL_ASSERT(format[5] == 'L');

        AppendToOutput("#0x%" PRIx64, instr->ImmMoveWide());

        if (instr->ShiftMoveWide() > 0) {

          AppendToOutput(", lsl #%d", 16 * instr->ShiftMoveWide());

          AppendToOutput(", lsl #%" PRId64, 16 * instr->ShiftMoveWide());

        }

      }

      return 8;
@@ -1418,7 +1418,7 @@ int Disassembler::SubstituteImmediateField(Instruction* instr, 
    }

    case 'F': {  // IFPSingle, IFPDouble or IFPFBits.

      if (format[3] == 'F') {  // IFPFbits.

        AppendToOutput("#%d", 64 - instr->FPScale());

        AppendToOutput("#%" PRId64, 64 - instr->FPScale());

        return 8;

      } else {

        AppendToOutput("#0x%" PRIx64 " (%.4f)", instr->ImmFP(),
@@ -1439,23 +1439,23 @@ int Disassembler::SubstituteImmediateField(Instruction* instr, 
      return 5;

    }

    case 'P': {  // IP - Conditional compare.

      AppendToOutput("#%d", instr->ImmCondCmp());

      AppendToOutput("#%" PRId64, instr->ImmCondCmp());

      return 2;

    }

    case 'B': {  // Bitfields.

      return SubstituteBitfieldImmediateField(instr, format);

    }

    case 'E': {  // IExtract.

      AppendToOutput("#%d", instr->ImmS());

      AppendToOutput("#%" PRId64, instr->ImmS());

      return 8;

    }

    case 'S': {  // IS - Test and branch bit.

      AppendToOutput("#%d", (instr->ImmTestBranchBit5() << 5) |

      AppendToOutput("#%" PRId64, (instr->ImmTestBranchBit5() << 5) |

                                  instr->ImmTestBranchBit40());

      return 2;

    }

    case 'D': {  // IDebug - HLT and BRK instructions.

      AppendToOutput("#0x%x", instr->ImmException());

      AppendToOutput("#0x%" PRIx64, instr->ImmException());

      return 6;

    }

    default: {
@@ -1626,12 +1626,12 @@ int Disassembler::SubstituteExtendField(Instruction* instr, 
      (((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) ||

       (instr->ExtendMode() == UXTX))) {

    if (instr->ImmExtendShift() > 0) {

      AppendToOutput(", lsl #%d", instr->ImmExtendShift());

      AppendToOutput(", lsl #%" PRId64, instr->ImmExtendShift());

    }

  } else {

    AppendToOutput(", %s", extend_mode[instr->ExtendMode()]);

    if (instr->ImmExtendShift() > 0) {

      AppendToOutput(" #%d", instr->ImmExtendShift());

      AppendToOutput(" #%" PRId64, instr->ImmExtendShift());

    }

  }

  return 3;
@@ -1660,7 +1660,7 @@ int Disassembler::SubstituteLSRegOffsetField(Instruction* instr, 
  if (!((ext == UXTX) && (shift == 0))) {

    AppendToOutput(", %s", extend_mode[ext]);

    if (shift != 0) {

      AppendToOutput(" #%d", instr->SizeLS());

      AppendToOutput(" #%" PRId64, instr->SizeLS());

    }

  }

  return 9;