Commit ffd9589e authored by Mark Cave-Ayland's avatar Mark Cave-Ayland
Browse files

apb: split simba PCI bridge into hw/pci-bridge/simba.c 



Move the QOM type and macros into a new include/hw/pci-bridge/simba.h
file, and add a new CONFIG_SIMBA Makefile.objs variable which is enabled
for sparc64-softmmu builds only.

Signed-off-by: default avatarMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
CC: Michael S. Tsirkin <mst@redhat.com>
CC: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: default avatarArtyom Tarasenko <atar4qemu@gmail.com>
parent 05b9ec96

default-configs/sparc64-softmmu.mak

+1 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ CONFIG_FDC=y 
CONFIG_IDE_ISA=y

CONFIG_IDE_CMD646=y

CONFIG_PCI_APB=y

CONFIG_SIMBA=y

CONFIG_SUNHME=y

CONFIG_MC146818RTC=y

CONFIG_ISA_TESTDEV=y

hw/pci-bridge/Makefile.objs

+2 −0
Original line number Diff line number Diff line
@@ -6,3 +6,5 @@ common-obj-$(CONFIG_IOH3420) += ioh3420.o 
common-obj-$(CONFIG_I82801B11) += i82801b11.o

# NewWorld PowerMac

common-obj-$(CONFIG_DEC_PCI) += dec.o

# Sun4u

common-obj-$(CONFIG_SIMBA) += simba.o

hw/pci-bridge/simba.c

0 → 100644
+101 −0
Original line number Diff line number Diff line 
/*

 * QEMU Simba PCI bridge

 *

 * Copyright (c) 2006 Fabrice Bellard

 * Copyright (c) 2012,2013 Artyom Tarasenko

 * Copyright (c) 2018 Mark Cave-Ayland

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */



#include "qemu/osdep.h"

#include "hw/pci/pci.h"

#include "hw/pci/pci_bridge.h"

#include "hw/pci/pci_bus.h"

#include "hw/pci-bridge/simba.h"



/*

 * Chipset docs:

 * APB: "Advanced PCI Bridge (APB) User's Manual",

 * http://www.sun.com/processors/manuals/805-1251.pdf

 */



static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)

{

    /*

     * command register:

     * According to PCI bridge spec, after reset

     *   bus master bit is off

     *   memory space enable bit is off

     * According to manual (805-1251.pdf).

     *   the reset value should be zero unless the boot pin is tied high

     *   (which is true) and thus it should be PCI_COMMAND_MEMORY.

     */

    PBMPCIBridge *br = PBM_PCI_BRIDGE(dev);



    pci_bridge_initfn(dev, TYPE_PCI_BUS);



    pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY);

    pci_set_word(dev->config + PCI_STATUS,

                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |

                 PCI_STATUS_DEVSEL_MEDIUM);



    /* Allow 32-bit IO addresses */

    pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32);

    pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32);

    pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff);

    pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff);



    pci_bridge_update_mappings(PCI_BRIDGE(br));

}



static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);

    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);



    k->realize = apb_pci_bridge_realize;

    k->exit = pci_bridge_exitfn;

    k->vendor_id = PCI_VENDOR_ID_SUN;

    k->device_id = PCI_DEVICE_ID_SUN_SIMBA;

    k->revision = 0x11;

    k->config_write = pci_bridge_write_config;

    k->is_bridge = 1;

    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);

    dc->reset = pci_bridge_reset;

    dc->vmsd = &vmstate_pci_device;

}



static const TypeInfo pbm_pci_bridge_info = {

    .name          = TYPE_PBM_PCI_BRIDGE,

    .parent        = TYPE_PCI_BRIDGE,

    .class_init    = pbm_pci_bridge_class_init,

    .instance_size = sizeof(PBMPCIBridge),

    .interfaces = (InterfaceInfo[]) {

        { INTERFACE_CONVENTIONAL_PCI_DEVICE },

        { },

    },

};



static void pbm_register_types(void)

{

    type_register_static(&pbm_pci_bridge_info);

}



type_init(pbm_register_types)

hw/pci-host/apb.c

+1 −61
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
#include "hw/pci/pci_host.h"

#include "hw/pci/pci_bridge.h"

#include "hw/pci/pci_bus.h"

#include "hw/pci-bridge/simba.h"

#include "hw/pci-host/apb.h"

#include "sysemu/sysemu.h"

#include "exec/address-spaces.h"
@@ -53,9 +54,6 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) 
 * Chipset docs:

 * PBM: "UltraSPARC IIi User's Manual",

 * http://www.sun.com/processors/manuals/805-0087.pdf

 *

 * APB: "Advanced PCI Bridge (APB) User's Manual",

 * http://www.sun.com/processors/manuals/805-1251.pdf

 */



#define PBM_PCI_IMR_MASK    0x7fffffff
@@ -348,35 +346,6 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level) 
    }

}



static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)

{

    /*

     * command register:

     * According to PCI bridge spec, after reset

     *   bus master bit is off

     *   memory space enable bit is off

     * According to manual (805-1251.pdf).

     *   the reset value should be zero unless the boot pin is tied high

     *   (which is true) and thus it should be PCI_COMMAND_MEMORY.

     */

    PBMPCIBridge *br = PBM_PCI_BRIDGE(dev);



    pci_bridge_initfn(dev, TYPE_PCI_BUS);



    pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY);

    pci_set_word(dev->config + PCI_STATUS,

                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |

                 PCI_STATUS_DEVSEL_MEDIUM);



    /* Allow 32-bit IO addresses */

    pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32);

    pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32);

    pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff);

    pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff);



    pci_bridge_update_mappings(PCI_BRIDGE(br));

}



static void pci_pbm_reset(DeviceState *d)

{

    APBState *s = APB_DEVICE(d);
@@ -564,39 +533,10 @@ static const TypeInfo pbm_host_info = { 
    .class_init    = pbm_host_class_init,

};



static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);

    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);



    k->realize = apb_pci_bridge_realize;

    k->exit = pci_bridge_exitfn;

    k->vendor_id = PCI_VENDOR_ID_SUN;

    k->device_id = PCI_DEVICE_ID_SUN_SIMBA;

    k->revision = 0x11;

    k->config_write = pci_bridge_write_config;

    k->is_bridge = 1;

    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);

    dc->reset = pci_bridge_reset;

    dc->vmsd = &vmstate_pci_device;

}



static const TypeInfo pbm_pci_bridge_info = {

    .name          = TYPE_PBM_PCI_BRIDGE,

    .parent        = TYPE_PCI_BRIDGE,

    .class_init    = pbm_pci_bridge_class_init,

    .instance_size = sizeof(PBMPCIBridge),

    .interfaces = (InterfaceInfo[]) {

        { INTERFACE_CONVENTIONAL_PCI_DEVICE },

        { },

    },

};



static void pbm_register_types(void)

{

    type_register_static(&pbm_host_info);

    type_register_static(&pbm_pci_host_info);

    type_register_static(&pbm_pci_bridge_info);

}



type_init(pbm_register_types)

include/hw/pci-bridge/simba.h

0 → 100644
+38 −0
Original line number Diff line number Diff line 
/*

 * QEMU Simba PCI bridge

 *

 * Copyright (c) 2006 Fabrice Bellard

 * Copyright (c) 2012,2013 Artyom Tarasenko

 * Copyright (c) 2017 Mark Cave-Ayland

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */



#include "qemu/osdep.h"

#include "hw/pci/pci_bridge.h"





typedef struct PBMPCIBridge {

    /*< private >*/

    PCIBridge parent_obj;

} PBMPCIBridge;



#define TYPE_PBM_PCI_BRIDGE "pbm-bridge"

#define PBM_PCI_BRIDGE(obj) \

    OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)