Unverified Commit ff9f31d9 authored by Xi Wang's avatar Xi Wang Committed by Palmer Dabbelt
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target/riscv: fix counter-enable checks in ctr() 



Access to a counter in U-mode is permitted only if the corresponding
bit is set in both mcounteren and scounteren.  The current code
ignores mcounteren and checks scounteren only for U-mode access.

Signed-off-by: default avatarXi Wang <xi.wang@gmail.com>
Reviewed-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 7d04ac38

target/riscv/csr.c

+9 −3
Original line number Diff line number Diff line
@@ -56,9 +56,15 @@ static int fs(CPURISCVState *env, int csrno) 
static int ctr(CPURISCVState *env, int csrno)

{

#if !defined(CONFIG_USER_ONLY)

    target_ulong ctr_en = env->priv == PRV_U ? env->scounteren :

                          env->priv == PRV_S ? env->mcounteren : -1U;

    if (!(ctr_en & (1 << (csrno & 31)))) {

    uint32_t ctr_en = ~0u;



    if (env->priv < PRV_M) {

        ctr_en &= env->mcounteren;

    }

    if (env->priv < PRV_S) {

        ctr_en &= env->scounteren;

    }

    if (!(ctr_en & (1u << (csrno & 31)))) {

        return -1;

    }

#endif