Commit fca3dad5 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging 



# gpg: Signature made Thu 25 Jan 2018 15:15:03 GMT
# gpg:                using RSA key 0xF30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>"
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier/tags/m68k-for-2.12-pull-request:
  target/m68k: add HMP command "info tlb"
  target/m68k: add pflush/ptest
  target/m68k: add moves
  target/m68k: add index parameter to gen_load()/gen_store() and Co.
  target/m68k: add Transparent Translation
  target/m68k: add MC68040 MMU
  accel/tcg: add size paremeter in tlb_fill()
  target/m68k: fix TCG variable double free

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents d2bc6e1f 2097dca6

accel/tcg/cputlb.c

+8 −5
Original line number Diff line number Diff line
@@ -880,7 +880,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) 
    if (unlikely(env->tlb_table[mmu_idx][index].addr_code !=

                 (addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)))) {

        if (!VICTIM_TLB_HIT(addr_read, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, MMU_INST_FETCH, mmu_idx, 0);

            tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);

        }

    }

    iotlbentry = &env->iotlb[mmu_idx][index];
@@ -928,7 +928,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) 
 * Otherwise the function will return, and there will be a valid

 * entry in the TLB for this access.

 */

void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,

void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,

                 uintptr_t retaddr)

{

    int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
@@ -938,7 +938,8 @@ void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, 
        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        /* TLB entry is for a different page */

        if (!VICTIM_TLB_HIT(addr_write, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);

            tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE,

                     mmu_idx, retaddr);

        }

    }

}
@@ -981,7 +982,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, 
    if ((addr & TARGET_PAGE_MASK)

        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if (!VICTIM_TLB_HIT(addr_write, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);

            tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE,

                     mmu_idx, retaddr);

        }

        tlb_addr = tlbe->addr_write & ~TLB_INVALID_MASK;

    }
@@ -995,7 +997,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, 


    /* Let the guest notice RMW on a write-only page.  */

    if (unlikely(tlbe->addr_read != (tlb_addr & ~TLB_NOTDIRTY))) {

        tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_LOAD, mmu_idx, retaddr);

        tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_LOAD,

                 mmu_idx, retaddr);

        /* Since we don't support reads and writes to different addresses,

           and we do have the proper page loaded for write, this shouldn't

           ever return.  But just in case, handle via stop-the-world.  */

accel/tcg/softmmu_template.h

+8 −6
Original line number Diff line number Diff line
@@ -124,7 +124,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, 
    if ((addr & TARGET_PAGE_MASK)

         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,

            tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE,

                     mmu_idx, retaddr);

        }

        tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
@@ -191,7 +191,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, 
    if ((addr & TARGET_PAGE_MASK)

         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,

            tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE,

                     mmu_idx, retaddr);

        }

        tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
@@ -283,7 +283,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, 
    if ((addr & TARGET_PAGE_MASK)

        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if (!VICTIM_TLB_HIT(addr_write, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);

            tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,

                     mmu_idx, retaddr);

        }

        tlb_addr = env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVALID_MASK;

    }
@@ -316,7 +317,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, 
        tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write;

        if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK))

            && !VICTIM_TLB_HIT(addr_write, page2)) {

            tlb_fill(ENV_GET_CPU(env), page2, MMU_DATA_STORE,

            tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE,

                     mmu_idx, retaddr);

        }
@@ -359,7 +360,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, 
    if ((addr & TARGET_PAGE_MASK)

        != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {

        if (!VICTIM_TLB_HIT(addr_write, addr)) {

            tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);

            tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE,

                     mmu_idx, retaddr);

        }

        tlb_addr = env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVALID_MASK;

    }
@@ -392,7 +394,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, 
        tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write;

        if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK))

            && !VICTIM_TLB_HIT(addr_write, page2)) {

            tlb_fill(ENV_GET_CPU(env), page2, MMU_DATA_STORE,

            tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE,

                     mmu_idx, retaddr);

        }

accel/tcg/user-exec.c

+1 −1
Original line number Diff line number Diff line
@@ -149,7 +149,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, 
    cc = CPU_GET_CLASS(cpu);

    /* see if it is an MMU fault */

    g_assert(cc->handle_mmu_fault);

    ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);

    ret = cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_IDX);



    if (ret == 0) {

        /* The MMU fault was handled without causing real CPU fault.

hmp-commands-info.hx

+1 −1
Original line number Diff line number Diff line
@@ -216,7 +216,7 @@ Show PCI information. 
ETEXI



#if defined(TARGET_I386) || defined(TARGET_SH4) || defined(TARGET_SPARC) || \

    defined(TARGET_PPC) || defined(TARGET_XTENSA)

    defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K)

    {

        .name       = "tlb",

        .args_type  = "",

include/exec/exec-all.h

+3 −3
Original line number Diff line number Diff line
@@ -253,7 +253,7 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, 
                  hwaddr paddr, int prot,

                  int mmu_idx, target_ulong size);

void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);

void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,

void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,

                 uintptr_t retaddr);

#else

static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
@@ -436,8 +436,8 @@ void tb_lock_reset(void); 
struct MemoryRegion *iotlb_to_region(CPUState *cpu,

                                     hwaddr index, MemTxAttrs attrs);



void tlb_fill(CPUState *cpu, target_ulong addr, MMUAccessType access_type,

              int mmu_idx, uintptr_t retaddr);

void tlb_fill(CPUState *cpu, target_ulong addr, int size,

              MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);



#endif