Commit fbd06e1e authored by Alex Bennée's avatar Alex Bennée Committed by Peter Maydell
Browse files

arm/translate-a64: add FP16 FRECPE 



Now we have added f16 during the re-factoring we can simply call the
helper.

Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-24-alex.bennee@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 5eb70735

target/arm/translate-a64.c

+8 −0
Original line number Diff line number Diff line
@@ -11311,6 +11311,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) 
    case 0x6d: /* FCMLE (zero) */

        handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);

        return;

    case 0x3d: /* FRECPE */

        break;

    case 0x18: /* FRINTN */

        need_rmode = true;

        only_in_vector = true;
@@ -11431,6 +11433,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) 
        case 0x3b: /* FCVTZS */

            gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);

            break;

        case 0x3d: /* FRECPE */

            gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);

            break;

        case 0x5a: /* FCVTNU */

        case 0x5b: /* FCVTMU */

        case 0x5c: /* FCVTAU */
@@ -11466,6 +11471,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) 
            case 0x3b: /* FCVTZS */

                gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);

                break;

            case 0x3d: /* FRECPE */

                gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);

                break;

            case 0x5a: /* FCVTNU */

            case 0x5b: /* FCVTMU */

            case 0x5c: /* FCVTAU */