Unverified Commit fb738839 authored by Michael Clark's avatar Michael Clark Committed by Palmer Dabbelt
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RISC-V: Use riscv prefix consistently on cpu helpers 



* Add riscv prefix to raise_exception function
* Add riscv prefix to CSR read/write functions
* Add riscv prefix to signal handler function
* Add riscv prefix to get fflags function
* Remove redundant declaration of riscv_cpu_init
  and rename cpu_riscv_init to riscv_cpu_init
* rename riscv_set_mode to riscv_cpu_set_mode

Signed-off-by: default avatarMichael Clark <mjc@sifive.com>
Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 7f2b5ff1

linux-user/riscv/signal.c

+2 −2
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env) 
        __put_user(env->fpr[i], &sc->fpr[i]);

    }



    uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/

    uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);

    __put_user(fcsr, &sc->fcsr);

}
@@ -159,7 +159,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc) 


    uint32_t fcsr;

    __get_user(fcsr, &sc->fcsr);

    csr_write_helper(env, fcsr, CSR_FCSR);

    riscv_csr_write(env, CSR_FCSR, fcsr);

}



static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)

target/riscv/cpu.h

+10 −11
Original line number Diff line number Diff line
@@ -256,7 +256,7 @@ int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, 
char *riscv_isa_string(RISCVCPU *cpu);

void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);



#define cpu_signal_handler cpu_riscv_signal_handler

#define cpu_signal_handler riscv_cpu_signal_handler

#define cpu_list riscv_cpu_list

#define cpu_mmu_index riscv_cpu_mmu_index
@@ -264,16 +264,15 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf); 
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);

#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */

#endif

void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);

void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);



void riscv_translate_init(void);

RISCVCPU *cpu_riscv_init(const char *cpu_model);

int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);

void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,

int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);

void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,

                                         uint32_t exception, uintptr_t pc);



target_ulong cpu_riscv_get_fflags(CPURISCVState *env);

void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);

target_ulong riscv_cpu_get_fflags(CPURISCVState *env);

void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);



#define TB_FLAGS_MMU_MASK   3

#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
@@ -293,13 +292,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 
int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,

                target_ulong new_value, target_ulong write_mask);



static inline void csr_write_helper(CPURISCVState *env, target_ulong val,

                                    int csrno)

static inline void riscv_csr_write(CPURISCVState *env, int csrno,

                                   target_ulong val)

{

    riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));

}



static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno)

static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)

{

    target_ulong val = 0;

    riscv_csrrw(env, csrno, &val, 0, 0);

target/riscv/cpu_helper.c

+5 −5
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) 
    return old;

}



void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)

void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)

{

    if (newpriv > PRV_M) {

        g_assert_not_reached();
@@ -366,7 +366,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 
        g_assert_not_reached();

    }

    env->badaddr = addr;

    do_raise_exception_err(env, cs->exception_index, retaddr);

    riscv_raise_exception(env, cs->exception_index, retaddr);

}



/* called by qemu's softmmu to fill the qemu tlb */
@@ -378,7 +378,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, 
    if (ret == TRANSLATE_FAIL) {

        RISCVCPU *cpu = RISCV_CPU(cs);

        CPURISCVState *env = &cpu->env;

        do_raise_exception_err(env, cs->exception_index, retaddr);

        riscv_raise_exception(env, cs->exception_index, retaddr);

    }

}
@@ -530,7 +530,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) 
        s = set_field(s, MSTATUS_SPP, env->priv);

        s = set_field(s, MSTATUS_SIE, 0);

        env->mstatus = s;

        riscv_set_mode(env, PRV_S);

        riscv_cpu_set_mode(env, PRV_S);

    } else {

        /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */

        env->pc = env->mtvec;
@@ -555,7 +555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) 
        s = set_field(s, MSTATUS_MPP, env->priv);

        s = set_field(s, MSTATUS_MIE, 0);

        env->mstatus = s;

        riscv_set_mode(env, PRV_M);

        riscv_cpu_set_mode(env, PRV_M);

    }

    /* TODO yield load reservation  */

#endif

target/riscv/csr.c

+4 −4
Original line number Diff line number Diff line
@@ -90,7 +90,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) 
        return -1;

    }

#endif

    *val = cpu_riscv_get_fflags(env);

    *val = riscv_cpu_get_fflags(env);

    return 0;

}
@@ -102,7 +102,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) 
    }

    env->mstatus |= MSTATUS_FS;

#endif

    cpu_riscv_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));

    riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));

    return 0;

}
@@ -136,7 +136,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) 
        return -1;

    }

#endif

    *val = (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)

    *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)

        | (env->frm << FSR_RD_SHIFT);

    return 0;

}
@@ -150,7 +150,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) 
    env->mstatus |= MSTATUS_FS;

#endif

    env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;

    cpu_riscv_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);

    riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);

    return 0;

}

target/riscv/fpu_helper.c

+3 −3
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
#include "exec/exec-all.h"

#include "exec/helper-proto.h"



target_ulong cpu_riscv_get_fflags(CPURISCVState *env)

target_ulong riscv_cpu_get_fflags(CPURISCVState *env)

{

    int soft = get_float_exception_flags(&env->fp_status);

    target_ulong hard = 0;
@@ -36,7 +36,7 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env) 
    return hard;

}



void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)

void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)

{

    int soft = 0;
@@ -73,7 +73,7 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) 
        softrm = float_round_ties_away;

        break;

    default:

        do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());

        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());

    }



    set_float_rounding_mode(softrm, &env->fp_status);