Commit f9c9cd63 authored by Philippe Mathieu-Daudé's avatar Philippe Mathieu-Daudé Committed by Aleksandar Markovic
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target/mips: Increase 'supported ISAs/ASEs' flag holder size 



Increase the size of insn_flags holder size to 64 bits. This is
needed for future extensions since existing bits are almost all used.

Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
parent 8bacd1ff

target/mips/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -811,7 +811,7 @@ struct CPUMIPSState { 
    int CCRes; /* Cycle count resolution/divisor */

    uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */

    uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */

    int insn_flags; /* Supported instruction set */

    uint64_t insn_flags; /* Supported instruction set */



    /* Fields up to this point are cleared by a CPU reset */

    struct {} end_reset_fields;

target/mips/internal.h

+1 −1
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ struct mips_def_t { 
    int32_t CP0_PageGrain_rw_bitmask;

    int32_t CP0_PageGrain;

    target_ulong CP0_EBaseWG_rw_bitmask;

    int insn_flags;

    uint64_t insn_flags;

    enum mips_mmu_types mmu_type;

};

target/mips/translate.c

+3 −3
Original line number Diff line number Diff line
@@ -1986,7 +1986,7 @@ typedef struct DisasContext { 
    target_ulong saved_pc;

    target_ulong page_start;

    uint32_t opcode;

    int insn_flags;

    uint64_t insn_flags;

    int32_t CP0_Config1;

    int32_t CP0_Config3;

    int32_t CP0_Config5;
@@ -2409,7 +2409,7 @@ static inline void check_dspr2(DisasContext *ctx) 








/* This code generates a "reserved instruction" exception if the









   CPU does not support the instruction set corresponding to flags. */









static inline void check_insn(DisasContext *ctx, int flags)









static inline void check_insn(DisasContext *ctx, uint64_t flags)









{









    if (unlikely(!(ctx->insn_flags & flags))) {









        generate_exception_end(ctx, EXCP_RI);








@@ -2419,7 +2419,7 @@ static inline void check_insn(DisasContext *ctx, int flags)







/* This code generates a "reserved instruction" exception if the









   CPU has corresponding flag set which indicates that the instruction









   has been removed. */









static inline void check_insn_opc_removed(DisasContext *ctx, int flags)









static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)









{









    if (unlikely(ctx->insn_flags & flags)) {









        generate_exception_end(ctx, EXCP_RI);