Commit f9b9db38 authored by Cédric Le Goater's avatar Cédric Le Goater Committed by David Gibson
Browse files

ppc/xive: export the TIMA memory accessors 



The PowerNV machine can perform indirect loads and stores on the TIMA
on behalf of another CPU. Give the controller the possibility to call
the TIMA memory accessors with a XiveTCTX of its choice.

Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Message-Id: <20190306085032.15744-4-clg@kaod.org>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 051e2973

hw/intc/xive.c

+18 −5
Original line number Diff line number Diff line
@@ -317,10 +317,9 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write) 
/*

 * TIMA MMIO handlers

 */

static void xive_tm_write(void *opaque, hwaddr offset,

                          uint64_t value, unsigned size)

void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,

                        unsigned size)

{

    XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);

    const XiveTmOp *xto;



    /*
@@ -356,9 +355,8 @@ static void xive_tm_write(void *opaque, hwaddr offset, 
    xive_tm_raw_write(tctx, offset, value, size);

}



static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)

uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)

{

    XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);

    const XiveTmOp *xto;



    /*
@@ -392,6 +390,21 @@ static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) 
    return xive_tm_raw_read(tctx, offset, size);

}



static void xive_tm_write(void *opaque, hwaddr offset,

                          uint64_t value, unsigned size)

{

    XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);



    xive_tctx_tm_write(tctx, offset, value, size);

}



static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)

{

    XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);



    return xive_tctx_tm_read(tctx, offset, size);

}



const MemoryRegionOps xive_tm_ops = {

    .read = xive_tm_read,

    .write = xive_tm_write,

include/hw/ppc/xive.h

+3 −0
Original line number Diff line number Diff line
@@ -410,6 +410,9 @@ void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon); 
#define XIVE_TM_USER_PAGE       0x3



extern const MemoryRegionOps xive_tm_ops;

void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,

                        unsigned size);

uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size);



void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);

Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);