Commit f8df9003 authored by Cédric Le Goater's avatar Cédric Le Goater Committed by David Gibson
Browse files

pnv/psi: move the ICSState qemu_irq array under the PSI device model 



Future changes of the ICSState object will remove the qemu_irq array
from under the interrupt controller model. Prepare ground for the PSI
interrupt sources and introduce a new one directly under the PSI
device model.

Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 734d9c89

hw/ppc/pnv_psi.c

+4 −3
Original line number Diff line number Diff line
@@ -207,7 +207,6 @@ static const uint64_t stat_bits[] = { 


void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state)

{

    ICSState *ics = &psi->ics;

    uint32_t xivr_reg;

    uint32_t stat_reg;

    uint32_t src;
@@ -227,14 +226,14 @@ void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state) 
        /* TODO: optimization, check mask here. That means

         * re-evaluating when unmasking

         */

        qemu_irq_raise(ics->qirqs[src]);

        qemu_irq_raise(psi->qirqs[src]);

    } else {

        psi->regs[stat_reg] &= ~stat_bits[irq];



        /* FSP and PSI are muxed so don't lower if either is still set */

        if (stat_reg != PSIHB_XSCOM_CR ||

            !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) {

            qemu_irq_lower(ics->qirqs[src]);

            qemu_irq_lower(psi->qirqs[src]);

        } else {

            state = true;

        }
@@ -491,6 +490,8 @@ static void pnv_psi_realize(DeviceState *dev, Error **errp) 
        ics_set_irq_type(ics, i, true);

    }



    psi->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);



    /* XSCOM region for PSI registers */

    pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops,

                psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE);

include/hw/ppc/pnv_psi.h

+1 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ typedef struct PnvPsi { 


    /* Interrupt generation */

    ICSState ics;

    qemu_irq *qirqs;



    /* Registers */

    uint64_t regs[PSIHB_XSCOM_MAX];