Commit f8cd1b02 authored by Mao Zhongyi's avatar Mao Zhongyi Committed by Michael S. Tsirkin
Browse files

pci: Convert to realize 



Convert i82801b11, io3130_upstream, io3130_downstream and
pcie_root_port devices to realize.

Cc: mst@redhat.com
Cc: marcel@redhat.com
Cc: armbru@redhat.com
Signed-off-by: default avatarMao Zhongyi <maozy.fnst@cn.fujitsu.com>
Reviewed-by: default avatarMarcel Apfelbaum <marcel@redhat.com>
Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
parent 27841278

hw/pci-bridge/i82801b11.c

+5 −6
Original line number Diff line number Diff line
@@ -59,24 +59,23 @@ typedef struct I82801b11Bridge { 
    /*< public >*/

} I82801b11Bridge;



static int i82801b11_bridge_initfn(PCIDevice *d)

static void i82801b11_bridge_realize(PCIDevice *d, Error **errp)

{

    int rc;



    pci_bridge_initfn(d, TYPE_PCI_BUS);



    rc = pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET,

                               I82801ba_SSVID_SVID, I82801ba_SSVID_SSID);

                               I82801ba_SSVID_SVID, I82801ba_SSVID_SSID,

                               errp);

    if (rc < 0) {

        goto err_bridge;

    }

    pci_config_set_prog_interface(d->config, PCI_CLASS_BRIDGE_PCI_INF_SUB);

    return 0;

    return;



err_bridge:

    pci_bridge_exitfn(d);



    return rc;

}



static const VMStateDescription i82801b11_bridge_dev_vmstate = {
@@ -96,7 +95,7 @@ static void i82801b11_bridge_class_init(ObjectClass *klass, void *data) 
    k->vendor_id = PCI_VENDOR_ID_INTEL;

    k->device_id = PCI_DEVICE_ID_INTEL_82801BA_11;

    k->revision = ICH9_D2P_A2_REVISION;

    k->init = i82801b11_bridge_initfn;

    k->realize = i82801b11_bridge_realize;

    k->config_write = pci_bridge_write_config;

    dc->vmsd = &i82801b11_bridge_dev_vmstate;

    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);

hw/pci-bridge/pcie_root_port.c

+9 −9
Original line number Diff line number Diff line
@@ -59,29 +59,30 @@ static void rp_realize(PCIDevice *d, Error **errp) 
    PCIDeviceClass *dc = PCI_DEVICE_GET_CLASS(d);

    PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);

    int rc;

    Error *local_err = NULL;



    pci_config_set_interrupt_pin(d->config, 1);

    pci_bridge_initfn(d, TYPE_PCIE_BUS);

    pcie_port_init_reg(d);



    rc = pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, rpc->ssid);

    rc = pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id,

                               rpc->ssid, errp);

    if (rc < 0) {

        error_setg(errp, "Can't init SSV ID, error %d", rc);

        error_append_hint(errp, "Can't init SSV ID, error %d\n", rc);

        goto err_bridge;

    }



    if (rpc->interrupts_init) {

        rc = rpc->interrupts_init(d, &local_err);

        rc = rpc->interrupts_init(d, errp);

        if (rc < 0) {

            error_propagate(errp, local_err);

            goto err_bridge;

        }

    }



    rc = pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT, p->port);

    rc = pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT,

                       p->port, errp);

    if (rc < 0) {

        error_setg(errp, "Can't add Root Port capability, error %d", rc);

        error_append_hint(errp, "Can't add Root Port capability, "

                          "error %d\n", rc);

        goto err_int;

    }
@@ -98,9 +99,8 @@ static void rp_realize(PCIDevice *d, Error **errp) 
    }



    rc = pcie_aer_init(d, PCI_ERR_VER, rpc->aer_offset,

                       PCI_ERR_SIZEOF, &local_err);

                       PCI_ERR_SIZEOF, errp);

    if (rc < 0) {

        error_propagate(errp, local_err);

        goto err;

    }

    pcie_aer_root_init(d);

hw/pci-bridge/xio3130_downstream.c

+9 −11
Original line number Diff line number Diff line
@@ -56,33 +56,33 @@ static void xio3130_downstream_reset(DeviceState *qdev) 
    pci_bridge_reset(qdev);

}



static int xio3130_downstream_initfn(PCIDevice *d)

static void xio3130_downstream_realize(PCIDevice *d, Error **errp)

{

    PCIEPort *p = PCIE_PORT(d);

    PCIESlot *s = PCIE_SLOT(d);

    int rc;

    Error *err = NULL;



    pci_bridge_initfn(d, TYPE_PCIE_BUS);

    pcie_port_init_reg(d);



    rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,

                  XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,

                  XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &err);

                  XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,

                  errp);

    if (rc < 0) {

        assert(rc == -ENOTSUP);

        error_report_err(err);

        goto err_bridge;

    }



    rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,

                               XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);

                               XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,

                               errp);

    if (rc < 0) {

        goto err_bridge;

    }



    rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,

                       p->port);

                       p->port, errp);

    if (rc < 0) {

        goto err_msi;

    }
@@ -98,13 +98,12 @@ static int xio3130_downstream_initfn(PCIDevice *d) 
    }



    rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,

                       PCI_ERR_SIZEOF, &err);

                       PCI_ERR_SIZEOF, errp);

    if (rc < 0) {

        error_report_err(err);

        goto err;

    }



    return 0;

    return;



err:

    pcie_chassis_del_slot(s);
@@ -114,7 +113,6 @@ err_msi: 
    msi_uninit(d);

err_bridge:

    pci_bridge_exitfn(d);

    return rc;

}



static void xio3130_downstream_exitfn(PCIDevice *d)
@@ -181,7 +179,7 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data) 
    k->is_express = 1;

    k->is_bridge = 1;

    k->config_write = xio3130_downstream_write_config;

    k->init = xio3130_downstream_initfn;

    k->realize = xio3130_downstream_realize;

    k->exit = xio3130_downstream_exitfn;

    k->vendor_id = PCI_VENDOR_ID_TI;

    k->device_id = PCI_DEVICE_ID_TI_XIO3130D;

hw/pci-bridge/xio3130_upstream.c

+9 −11
Original line number Diff line number Diff line
@@ -53,32 +53,32 @@ static void xio3130_upstream_reset(DeviceState *qdev) 
    pcie_cap_deverr_reset(d);

}



static int xio3130_upstream_initfn(PCIDevice *d)

static void xio3130_upstream_realize(PCIDevice *d, Error **errp)

{

    PCIEPort *p = PCIE_PORT(d);

    int rc;

    Error *err = NULL;



    pci_bridge_initfn(d, TYPE_PCIE_BUS);

    pcie_port_init_reg(d);



    rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,

                  XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,

                  XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &err);

                  XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,

                  errp);

    if (rc < 0) {

        assert(rc == -ENOTSUP);

        error_report_err(err);

        goto err_bridge;

    }



    rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,

                               XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);

                               XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,

                               errp);

    if (rc < 0) {

        goto err_bridge;

    }



    rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,

                       p->port);

                       p->port, errp);

    if (rc < 0) {

        goto err_msi;

    }
@@ -86,13 +86,12 @@ static int xio3130_upstream_initfn(PCIDevice *d) 
    pcie_cap_deverr_init(d);



    rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,

                       PCI_ERR_SIZEOF, &err);

                       PCI_ERR_SIZEOF, errp);

    if (rc < 0) {

        error_report_err(err);

        goto err;

    }



    return 0;

    return;



err:

    pcie_cap_exit(d);
@@ -100,7 +99,6 @@ err_msi: 
    msi_uninit(d);

err_bridge:

    pci_bridge_exitfn(d);

    return rc;

}



static void xio3130_upstream_exitfn(PCIDevice *d)
@@ -153,7 +151,7 @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data) 
    k->is_express = 1;

    k->is_bridge = 1;

    k->config_write = xio3130_upstream_write_config;

    k->init = xio3130_upstream_initfn;

    k->realize = xio3130_upstream_realize;

    k->exit = xio3130_upstream_exitfn;

    k->vendor_id = PCI_VENDOR_ID_TI;

    k->device_id = PCI_DEVICE_ID_TI_XIO3130U;

hw/pci/pci_bridge.c

+3 −4
Original line number Diff line number Diff line
@@ -41,15 +41,14 @@ 
#define PCI_SSVID_SSID          6



int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,

                          uint16_t svid, uint16_t ssid)

                          uint16_t svid, uint16_t ssid,

                          Error **errp)

{

    int pos;

    Error *local_err = NULL;



    pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset,

                             PCI_SSVID_SIZEOF, &local_err);

                             PCI_SSVID_SIZEOF, errp);

    if (pos < 0) {

        error_report_err(local_err);

        return pos;

    }