Commit f72dbf3d authored by Rob Herring's avatar Rob Herring Committed by Peter Maydell
Browse files

pl011: fix incorrect logic to set the RXFF flag 



The receive fifo full bit should be set when 1 character is received and
the fifo is disabled or when 16 characters are in the fifo.

Signed-off-by: default avatarRob Herring <rob.herring@linaro.org>
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Message-id: 1395166721-15716-4-git-send-email-robherring2@gmail.com
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent ce8f0905

hw/char/pl011.c

+1 −1
Original line number Diff line number Diff line
@@ -221,7 +221,7 @@ static void pl011_put_fifo(void *opaque, uint32_t value) 
    s->read_fifo[slot] = value;

    s->read_count++;

    s->flags &= ~PL011_FLAG_RXFE;

    if (s->cr & 0x10 || s->read_count == 16) {

    if (!(s->lcr & 0x10) || s->read_count == 16) {

        s->flags |= PL011_FLAG_RXFF;

    }

    if (s->read_count == s->read_trigger) {