Commit f713d6ad authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg: Add qemu_ld_st_i32/64 



Step two in the transition, adding the new ldst opcodes.  Keep the old
opcodes around until all backends support the new opcodes.

Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent 6c5f4ead

tcg/README

+19 −24
Original line number Diff line number Diff line
@@ -412,30 +412,25 @@ current TB was linked to this TB. Otherwise execute the next 
instructions. Only indices 0 and 1 are valid and tcg_gen_goto_tb may be issued

at most once with each slot index per TB.



* qemu_ld8u t0, t1, flags

qemu_ld8s t0, t1, flags

qemu_ld16u t0, t1, flags

qemu_ld16s t0, t1, flags

qemu_ld32 t0, t1, flags

qemu_ld32u t0, t1, flags

qemu_ld32s t0, t1, flags

qemu_ld64 t0, t1, flags



Load data at the QEMU CPU address t1 into t0. t1 has the QEMU CPU address

type. 'flags' contains the QEMU memory index (selects user or kernel access)

for example.



Note that "qemu_ld32" implies a 32-bit result, while "qemu_ld32u" and

"qemu_ld32s" imply a 64-bit result appropriately extended from 32 bits.



* qemu_st8 t0, t1, flags

qemu_st16 t0, t1, flags

qemu_st32 t0, t1, flags

qemu_st64 t0, t1, flags



Store the data t0 at the QEMU CPU Address t1. t1 has the QEMU CPU

address type. 'flags' contains the QEMU memory index (selects user or

kernel access) for example.

* qemu_ld_i32/i64 t0, t1, flags, memidx

* qemu_st_i32/i64 t0, t1, flags, memidx



Load data at the guest address t1 into t0, or store data in t0 at guest

address t1.  The _i32/_i64 size applies to the size of the input/output

register t0 only.  The address t1 is always sized according to the guest,

and the width of the memory operation is controlled by flags.



Both t0 and t1 may be split into little-endian ordered pairs of registers

if dealing with 64-bit quantities on a 32-bit host.



The memidx selects the qemu tlb index to use (e.g. user or kernel access).

The flags are the TCGMemOp bits, selecting the sign, width, and endianness

of the memory access.



For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a

64-bit memory access specified in flags.



*********



Note 1: Some shortcuts are defined when the last operand is known to be

a constant (e.g. addi for add, movi for mov).

tcg/aarch64/tcg-target.h

+2 −0
Original line number Diff line number Diff line
@@ -96,6 +96,8 @@ enum { 
    TCG_AREG0 = TCG_REG_X19,

};



#define TCG_TARGET_HAS_new_ldst         0



static inline void flush_icache_range(uintptr_t start, uintptr_t stop)

{

    __builtin___clear_cache((char *)start, (char *)stop);

tcg/arm/tcg-target.h

+2 −0
Original line number Diff line number Diff line
@@ -85,6 +85,8 @@ extern bool use_idiv_instructions; 
#define TCG_TARGET_HAS_div_i32          use_idiv_instructions

#define TCG_TARGET_HAS_rem_i32          0



#define TCG_TARGET_HAS_new_ldst         0



extern bool tcg_target_deposit_valid(int ofs, int len);

#define TCG_TARGET_deposit_i32_valid  tcg_target_deposit_valid

tcg/i386/tcg-target.h

+2 −0
Original line number Diff line number Diff line
@@ -130,6 +130,8 @@ typedef enum { 
#define TCG_TARGET_HAS_mulsh_i64        0

#endif



#define TCG_TARGET_HAS_new_ldst         0



#define TCG_TARGET_deposit_i32_valid(ofs, len) \

    (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \

     ((ofs) == 0 && (len) == 16))

tcg/ia64/tcg-target.h

+2 −0
Original line number Diff line number Diff line
@@ -151,6 +151,8 @@ typedef enum { 
#define TCG_TARGET_HAS_mulsh_i32        0

#define TCG_TARGET_HAS_mulsh_i64        0



#define TCG_TARGET_HAS_new_ldst         0



#define TCG_TARGET_deposit_i32_valid(ofs, len) ((len) <= 16)

#define TCG_TARGET_deposit_i64_valid(ofs, len) ((len) <= 16)