Commit f634151b authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170108' into staging 



TCG host support for mips64

# gpg: Signature made Sun 08 Jan 2017 17:52:17 GMT
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-tcg-20170108:
  translate-all: Avoid -Werror=switch-bool
  tcg-mips: Adjust qemu_ld/st for mips64
  tcg-mips: Adjust calling conventions for mips64
  tcg-mips: Add tcg unwind info
  tcg-mips: Adjust prologue for mips64
  tcg-mips: Adjust load/store functions for mips64
  tcg-mips: Adjust move functions for mips64
  tcg-mips: Add bswap32u and bswap64
  tcg-mips: Support 64-bit opcodes
  tcg-mips: Add mips64 opcodes
  tcg-mips: Move bswap code to a subroutine

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 77424a45 f68808c7

tcg/mips/tcg-target.h

+56 −4
Original line number Diff line number Diff line
@@ -27,6 +27,14 @@ 
#ifndef MIPS_TCG_TARGET_H

#define MIPS_TCG_TARGET_H



#if _MIPS_SIM == _ABIO32

# define TCG_TARGET_REG_BITS 32

#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64

# define TCG_TARGET_REG_BITS 64

#else

# error "Unknown ABI"

#endif



#define TCG_TARGET_INSN_UNIT_SIZE 4

#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16

#define TCG_TARGET_NB_REGS 32
@@ -70,8 +78,12 @@ typedef enum { 
} TCGReg;



/* used for function call generation */

#define TCG_TARGET_STACK_ALIGN 8

#define TCG_TARGET_STACK_ALIGN        16

#if _MIPS_SIM == _ABIO32

# define TCG_TARGET_CALL_STACK_OFFSET 16

#else

# define TCG_TARGET_CALL_STACK_OFFSET 0

#endif

#define TCG_TARGET_CALL_ALIGN_ARGS    1



/* MOVN/MOVZ instructions detection */
@@ -117,21 +129,61 @@ extern bool use_mips32r2_instructions; 
#define TCG_TARGET_HAS_muls2_i32        (!use_mips32r6_instructions)

#define TCG_TARGET_HAS_muluh_i32        1

#define TCG_TARGET_HAS_mulsh_i32        1

#define TCG_TARGET_HAS_bswap32_i32      1



#if TCG_TARGET_REG_BITS == 64

#define TCG_TARGET_HAS_add2_i32         0

#define TCG_TARGET_HAS_sub2_i32         0

#define TCG_TARGET_HAS_extrl_i64_i32    1

#define TCG_TARGET_HAS_extrh_i64_i32    1

#define TCG_TARGET_HAS_div_i64          1

#define TCG_TARGET_HAS_rem_i64          1

#define TCG_TARGET_HAS_not_i64          1

#define TCG_TARGET_HAS_nor_i64          1

#define TCG_TARGET_HAS_andc_i64         0

#define TCG_TARGET_HAS_orc_i64          0

#define TCG_TARGET_HAS_eqv_i64          0

#define TCG_TARGET_HAS_nand_i64         0

#define TCG_TARGET_HAS_add2_i64         0

#define TCG_TARGET_HAS_sub2_i64         0

#define TCG_TARGET_HAS_mulu2_i64        (!use_mips32r6_instructions)

#define TCG_TARGET_HAS_muls2_i64        (!use_mips32r6_instructions)

#define TCG_TARGET_HAS_muluh_i64        1

#define TCG_TARGET_HAS_mulsh_i64        1

#define TCG_TARGET_HAS_ext32s_i64       1

#define TCG_TARGET_HAS_ext32u_i64       1

#endif



/* optional instructions detected at runtime */

#define TCG_TARGET_HAS_movcond_i32      use_movnz_instructions

#define TCG_TARGET_HAS_bswap16_i32      use_mips32r2_instructions

#define TCG_TARGET_HAS_bswap32_i32      use_mips32r2_instructions

#define TCG_TARGET_HAS_deposit_i32      use_mips32r2_instructions

#define TCG_TARGET_HAS_ext8s_i32        use_mips32r2_instructions

#define TCG_TARGET_HAS_ext16s_i32       use_mips32r2_instructions

#define TCG_TARGET_HAS_rot_i32          use_mips32r2_instructions



#if TCG_TARGET_REG_BITS == 64

#define TCG_TARGET_HAS_movcond_i64      use_movnz_instructions

#define TCG_TARGET_HAS_bswap16_i64      use_mips32r2_instructions

#define TCG_TARGET_HAS_bswap32_i64      use_mips32r2_instructions

#define TCG_TARGET_HAS_bswap64_i64      use_mips32r2_instructions

#define TCG_TARGET_HAS_deposit_i64      use_mips32r2_instructions

#define TCG_TARGET_HAS_ext8s_i64        use_mips32r2_instructions

#define TCG_TARGET_HAS_ext16s_i64       use_mips32r2_instructions

#define TCG_TARGET_HAS_rot_i64          use_mips32r2_instructions

#endif



/* optional instructions automatically implemented */

#define TCG_TARGET_HAS_neg_i32          0 /* sub  rd, zero, rt   */

#define TCG_TARGET_HAS_ext8u_i32        0 /* andi rt, rs, 0xff   */

#define TCG_TARGET_HAS_ext16u_i32       0 /* andi rt, rs, 0xffff */



#if TCG_TARGET_REG_BITS == 64

#define TCG_TARGET_HAS_neg_i64          0 /* sub  rd, zero, rt   */

#define TCG_TARGET_HAS_ext8u_i64        0 /* andi rt, rs, 0xff   */

#define TCG_TARGET_HAS_ext16u_i64       0 /* andi rt, rs, 0xffff */

#endif



#ifdef __OpenBSD__

#include <machine/sysarch.h>

#else

tcg/mips/tcg-target.inc.c

+921 −249

File changed.

Preview size limit exceeded, changes collapsed.

translate-all.c

+1 −1
Original line number Diff line number Diff line
@@ -753,7 +753,7 @@ static inline void *alloc_code_gen_buffer(void) 
        size_t size2;

        void *buf2 = mmap(NULL, size + qemu_real_host_page_size,

                          PROT_NONE, flags, -1, 0);

        switch (buf2 != MAP_FAILED) {

        switch ((int)(buf2 != MAP_FAILED)) {

        case 1:

            if (!cross_256mb(buf2, size)) {

                /* Success!  Use the new buffer.  */