Commit f5d9c108 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by David Gibson
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ppc: Properly tag the translation cache based on MMU mode 



We used to always flush the TLB when changing relocation mode in
MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data).

We don't anymore since we have split mmu_idx for instruction and data.

However, since we hard code the mmu_idx in the translated code, we
now need to also make sure MSR:IR and MSR:DR are part of the hflags
used to tag translated code, so that we use different translated
code for different MMU settings.

Darwin gets hurt by this problem.

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 88655881

target-ppc/helper_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@ static inline void hreg_compute_hflags(CPUPPCState *env) 
    /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */

    hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |

        (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |

        (1 << MSR_LE) | (1 << MSR_VSX);

        (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);

    hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;

    hreg_compute_mem_idx(env);

    env->hflags = env->msr & hflags_mask;