Commit f4df2210 authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn() 



Refactor to avoid passing a CPUARMState * to disas_arm_insn(). To do this
we move the "read insn from memory" code to the callsite and pass the
insn to the function instead.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Message-id: 1414524244-20316-6-git-send-email-peter.maydell@linaro.org
Reviewed-by: default avatarClaudio Fontana <claudio.fontana@huawei.com>
parent 7dcc1f89

target-arm/translate.c

+5 −6
Original line number Diff line number Diff line
@@ -7560,18 +7560,15 @@ static void gen_srs(DisasContext *s, 
    tcg_temp_free_i32(addr);

}



static void disas_arm_insn(CPUARMState * env, DisasContext *s)

static void disas_arm_insn(DisasContext *s, unsigned int insn)

{

    unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;

    unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh;

    TCGv_i32 tmp;

    TCGv_i32 tmp2;

    TCGv_i32 tmp3;

    TCGv_i32 addr;

    TCGv_i64 tmp64;



    insn = arm_ldl_code(env, s->pc, s->bswap_code);

    s->pc += 4;



    /* M variants do not implement ARM mode.  */

    if (arm_dc_feature(s, ARM_FEATURE_M)) {

        goto illegal_op;
@@ -11199,7 +11196,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, 
                }

            }

        } else {

            disas_arm_insn(env, dc);

            unsigned int insn = arm_ldl_code(env, dc->pc, dc->bswap_code);

            dc->pc += 4;

            disas_arm_insn(dc, insn);

        }



        if (dc->condjmp && !dc->is_jmp) {