Commit f4d1414a authored by Stafford Horne's avatar Stafford Horne
Browse files

target/openrisc: Support non-busy idle state using PMR SPR 



The OpenRISC architecture has the Power Management Register (PMR)
special purpose register to manage cpu power states.  The interesting
modes are:

 * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt
 * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt
 * Suspend Model (SUME) - Stop cpu and all units - wake on reset

The linux kernel will set DME when idle.

This patch implements the PMR SPR and halts the qemu cpu when there is a
change to DME or SME.  This means that openrisc qemu in no longer peggs
a host cpu at 100%.

In order for this to work we need to kick the CPU when timers are
expired.  Update the cpu timer to kick the cpu upon each timer event.

Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
Signed-off-by: default avatarStafford Horne <shorne@gmail.com>
parent 48a1b62b

hw/openrisc/cputimer.c

+1 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) 
    }

    next = now + (uint64_t)wait * TIMER_PERIOD;

    timer_mod(cpu->env.timer, next);

    qemu_cpu_kick(CPU(cpu));

}



void cpu_openrisc_count_start(OpenRISCCPU *cpu)

target/openrisc/cpu.c

+2 −1
Original line number Diff line number Diff line
@@ -51,7 +51,8 @@ static void openrisc_cpu_reset(CPUState *s) 
    cpu->env.lock_addr = -1;

    s->exception_index = -1;



    cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;

    cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |

                   UPR_PMP;

    cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));

    cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));

target/openrisc/cpu.h

+10 −0
Original line number Diff line number Diff line
@@ -140,6 +140,15 @@ enum { 
    IMMUCFGR_HTR = (1 << 11),

};



/* Power management register */

enum {

    PMR_SDF = (15 << 0),

    PMR_DME = (1 << 4),

    PMR_SME = (1 << 5),

    PMR_DCGE = (1 << 6),

    PMR_SUME = (1 << 7),

};



/* Float point control status register */

enum {

    FPCSR_FPEE = 1,
@@ -284,6 +293,7 @@ typedef struct CPUOpenRISCState { 
    uint32_t immucfgr;        /* IMMU configure register */

    uint32_t esr;             /* Exception supervisor register */

    uint32_t evbar;           /* Exception vector base address register */

    uint32_t pmr;             /* Power Management Register */

    uint32_t fpcsr;           /* Float register */

    float_status fp_status;

target/openrisc/interrupt.c

+2 −0
Original line number Diff line number Diff line
@@ -60,6 +60,8 @@ void openrisc_cpu_do_interrupt(CPUState *cs) 
    env->sr |= SR_SM;

    env->sr &= ~SR_IEE;

    env->sr &= ~SR_TEE;

    env->pmr &= ~PMR_DME;

    env->pmr &= ~PMR_SME;

    env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;

    env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;

    env->lock_addr = -1;

target/openrisc/machine.c

+1 −0
Original line number Diff line number Diff line
@@ -138,6 +138,7 @@ static const VMStateDescription vmstate_env = { 
        VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState),

        VMSTATE_UINT32(immucfgr, CPUOpenRISCState),

        VMSTATE_UINT32(evbar, CPUOpenRISCState),

        VMSTATE_UINT32(pmr, CPUOpenRISCState),

        VMSTATE_UINT32(esr, CPUOpenRISCState),

        VMSTATE_UINT32(fpcsr, CPUOpenRISCState),

        VMSTATE_UINT64(mac, CPUOpenRISCState),