Commit f478847f authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Remove writefn from TTBR0_EL3 



The EL3 version of this register does not include an ASID,
and so the tlb_flush performed by vmsa_ttbr_write is not needed.

Reviewed-by: default avatarAaron Lindsay <aaron@os.amperecomputing.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Message-id: 20181019015617.22583-2-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent e2c0c4ee

target/arm/helper.c

+1 −1
Original line number Diff line number Diff line
@@ -4312,7 +4312,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { 
      .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },

    { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,

      .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,

      .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,

      .access = PL3_RW, .resetvalue = 0,

      .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },

    { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,

      .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,