Commit f40385c9 authored by Max Filippov's avatar Max Filippov
Browse files

target/xtensa: check zero overhead loop alignment



ISA book documents that the first instruction of zero overhead loop
must fit completely into naturally aligned region of an instruction
fetch unit size. Check that condition and log a message if it's
violated.

Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
parent e3800998
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+1 −0
Original line number Diff line number Diff line
@@ -369,6 +369,7 @@ struct XtensaConfig {
    unsigned nareg;
    int excm_level;
    int ndepc;
    unsigned inst_fetch_width;
    uint32_t vecbase;
    uint32_t exception_vector[EXC_MAX];
    unsigned ninterrupt;
+1 −0
Original line number Diff line number Diff line
@@ -456,6 +456,7 @@
    .options = XTENSA_OPTIONS, \
    .nareg = XCHAL_NUM_AREGS, \
    .ndepc = (XCHAL_XEA_VERSION >= 2), \
    .inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \
    EXCEPTIONS_SECTION, \
    INTERRUPTS_SECTION, \
    TLB_SECTION, \
+7 −0
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@@ -970,6 +970,13 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
    }

    dc->next_pc = dc->pc + len;
    if (xtensa_option_enabled(dc->config, XTENSA_OPTION_LOOP) &&
        dc->lbeg == dc->pc &&
        ((dc->pc ^ (dc->next_pc - 1)) & -dc->config->inst_fetch_width)) {
        qemu_log_mask(LOG_GUEST_ERROR,
                      "unaligned first instruction of a loop (pc = %08x)\n",
                      dc->pc);
    }
    for (i = 1; i < len; ++i) {
        b[i] = cpu_ldub_code(env, dc->pc + i);
    }