Commit f400be18 authored by David Hildenbrand's avatar David Hildenbrand Committed by Cornelia Huck
Browse files

s390x/tcg: implement Interlocked-Access Facility 2 



With this facility, OI/OIY, NI/NIY and XI/XIY are atomic. All operate on
one byte (MO_UB). Emulate old behavior.

Signed-off-by: default avatarDavid Hildenbrand <david@redhat.com>
Message-Id: <20171208160207.26494-8-david@redhat.com>
Signed-off-by: default avatarCornelia Huck <cohuck@redhat.com>
parent 0e9383bc

target/s390x/cpu_models.c

+1 −0
Original line number Diff line number Diff line
@@ -842,6 +842,7 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm) 
        S390_FEAT_STFLE_45,

        S390_FEAT_STFLE_49,

        S390_FEAT_LOCAL_TLB_CLEARING,

        S390_FEAT_INTERLOCKED_ACCESS_2,

        S390_FEAT_STFLE_53,

        S390_FEAT_MSA_EXT_5,

        S390_FEAT_MSA_EXT_3,

target/s390x/insn-data.def

+6 −6
Original line number Diff line number Diff line
@@ -99,8 +99,8 @@ 
    D(0xa505, NIHL,    RI_a,  Z,   r1_o, i2_16u, r1, 0, andi, 0, 0x1020)

    D(0xa506, NILH,    RI_a,  Z,   r1_o, i2_16u, r1, 0, andi, 0, 0x1010)

    D(0xa507, NILL,    RI_a,  Z,   r1_o, i2_16u, r1, 0, andi, 0, 0x1000)

    C(0x9400, NI,      SI,    Z,   m1_8u, i2_8u, new, m1_8, and, nz64)

    C(0xeb54, NIY,     SIY,   LD,  m1_8u, i2_8u, new, m1_8, and, nz64)

    D(0x9400, NI,      SI,    Z,   la1, i2_8u, new, 0, ni, nz64, MO_UB)

    D(0xeb54, NIY,     SIY,   LD,  la1, i2_8u, new, 0, ni, nz64, MO_UB)



/* BRANCH AND SAVE */

    C(0x0d00, BASR,    RR_a,  Z,   0, r2_nz, r1, 0, bas, 0)
@@ -357,8 +357,8 @@ 
/* EXCLUSIVE OR IMMEDIATE */

    D(0xc006, XIHF,    RIL_a, EI,  r1_o, i2_32u, r1, 0, xori, 0, 0x2020)

    D(0xc007, XILF,    RIL_a, EI,  r1_o, i2_32u, r1, 0, xori, 0, 0x2000)

    C(0x9700, XI,      SI,    Z,   m1_8u, i2_8u, new, m1_8, xor, nz64)

    C(0xeb57, XIY,     SIY,   LD,  m1_8u, i2_8u, new, m1_8, xor, nz64)

    D(0x9700, XI,      SI,    Z,   la1, i2_8u, new, 0, xi, nz64, MO_UB)

    D(0xeb57, XIY,     SIY,   LD,  la1, i2_8u, new, 0, xi, nz64, MO_UB)



/* EXECUTE */

    C(0x4400, EX,      RX_a,  Z,   0, a2, 0, 0, ex, 0)
@@ -698,8 +698,8 @@ 
    D(0xa509, OIHL,    RI_a,  Z,   r1_o, i2_16u, r1, 0, ori, 0, 0x1020)

    D(0xa50a, OILH,    RI_a,  Z,   r1_o, i2_16u, r1, 0, ori, 0, 0x1010)

    D(0xa50b, OILL,    RI_a,  Z,   r1_o, i2_16u, r1, 0, ori, 0, 0x1000)

    C(0x9600, OI,      SI,    Z,   m1_8u, i2_8u, new, m1_8, or, nz64)

    C(0xeb56, OIY,     SIY,   LD,  m1_8u, i2_8u, new, m1_8, or, nz64)

    D(0x9600, OI,      SI,    Z,   la1, i2_8u, new, 0, oi, nz64, MO_UB)

    D(0xeb56, OIY,     SIY,   LD,  la1, i2_8u, new, 0, oi, nz64, MO_UB)



/* PACK */

    /* Really format SS_b, but we pack both lengths into one argument

target/s390x/translate.c

+63 −0
Original line number Diff line number Diff line
@@ -1427,6 +1427,27 @@ static ExitStatus op_andi(DisasContext *s, DisasOps *o) 
    return NO_EXIT;

}



static ExitStatus op_ni(DisasContext *s, DisasOps *o)

{

    o->in1 = tcg_temp_new_i64();



    if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {

        tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);

    } else {

        /* Perform the atomic operation in memory. */

        tcg_gen_atomic_fetch_and_i64(o->in1, o->addr1, o->in2, get_mem_index(s),

                                     s->insn->data);

    }



    /* Recompute also for atomic case: needed for setting CC. */

    tcg_gen_and_i64(o->out, o->in1, o->in2);



    if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {

        tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);

    }

    return NO_EXIT;

}



static ExitStatus op_bas(DisasContext *s, DisasOps *o)

{

    tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
@@ -3378,6 +3399,27 @@ static ExitStatus op_ori(DisasContext *s, DisasOps *o) 
    return NO_EXIT;

}



static ExitStatus op_oi(DisasContext *s, DisasOps *o)

{

    o->in1 = tcg_temp_new_i64();



    if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {

        tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);

    } else {

        /* Perform the atomic operation in memory. */

        tcg_gen_atomic_fetch_or_i64(o->in1, o->addr1, o->in2, get_mem_index(s),

                                    s->insn->data);

    }



    /* Recompute also for atomic case: needed for setting CC. */

    tcg_gen_or_i64(o->out, o->in1, o->in2);



    if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {

        tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);

    }

    return NO_EXIT;

}



static ExitStatus op_pack(DisasContext *s, DisasOps *o)

{

    TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
@@ -4643,6 +4685,27 @@ static ExitStatus op_xori(DisasContext *s, DisasOps *o) 
    return NO_EXIT;

}



static ExitStatus op_xi(DisasContext *s, DisasOps *o)

{

    o->in1 = tcg_temp_new_i64();



    if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {

        tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);

    } else {

        /* Perform the atomic operation in memory. */

        tcg_gen_atomic_fetch_xor_i64(o->in1, o->addr1, o->in2, get_mem_index(s),

                                     s->insn->data);

    }



    /* Recompute also for atomic case: needed for setting CC. */

    tcg_gen_xor_i64(o->out, o->in1, o->in2);



    if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {

        tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);

    }

    return NO_EXIT;

}



static ExitStatus op_zero(DisasContext *s, DisasOps *o)

{

    o->out = tcg_const_i64(0);