Commit f34ec0f6 authored by Richard Henderson's avatar Richard Henderson
Browse files

target/ppc: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128 



Reviewed-by: default avatarEmilio G. Cota <cota@braap.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent 62823083

target/ppc/helper.h

+1 −1
Original line number Diff line number Diff line
@@ -800,7 +800,7 @@ DEF_HELPER_4(dscliq, void, env, fprp, fprp, i32) 
DEF_HELPER_1(tbegin, void, env)

DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, env)



#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128)

#ifdef TARGET_PPC64

DEF_HELPER_FLAGS_3(lq_le_parallel, TCG_CALL_NO_WG, i64, env, tl, i32)

DEF_HELPER_FLAGS_3(lq_be_parallel, TCG_CALL_NO_WG, i64, env, tl, i32)

DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG,

target/ppc/mem_helper.c

+28 −5
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include "exec/cpu_ldst.h"

#include "tcg.h"

#include "internal.h"

#include "qemu/atomic128.h"



//#define DEBUG_OP
@@ -215,11 +216,15 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg, 
    return i;

}



#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128)

#ifdef TARGET_PPC64

uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr,

                               uint32_t opidx)

{

    Int128 ret = helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC());

    Int128 ret;



    /* We will have raised EXCP_ATOMIC from the translator.  */

    assert(HAVE_ATOMIC128);

    ret = helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC());

    env->retxh = int128_gethi(ret);

    return int128_getlo(ret);

}
@@ -227,7 +232,11 @@ uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr, 
uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr,

                               uint32_t opidx)

{

    Int128 ret = helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC());

    Int128 ret;



    /* We will have raised EXCP_ATOMIC from the translator.  */

    assert(HAVE_ATOMIC128);

    ret = helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC());

    env->retxh = int128_gethi(ret);

    return int128_getlo(ret);

}
@@ -235,14 +244,22 @@ uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr, 
void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr,

                            uint64_t lo, uint64_t hi, uint32_t opidx)

{

    Int128 val = int128_make128(lo, hi);

    Int128 val;



    /* We will have raised EXCP_ATOMIC from the translator.  */

    assert(HAVE_ATOMIC128);

    val = int128_make128(lo, hi);

    helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC());

}



void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr,

                            uint64_t lo, uint64_t hi, uint32_t opidx)

{

    Int128 val = int128_make128(lo, hi);

    Int128 val;



    /* We will have raised EXCP_ATOMIC from the translator.  */

    assert(HAVE_ATOMIC128);

    val = int128_make128(lo, hi);

    helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC());

}
@@ -252,6 +269,9 @@ uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr, 
{

    bool success = false;



    /* We will have raised EXCP_ATOMIC from the translator.  */

    assert(HAVE_CMPXCHG128);



    if (likely(addr == env->reserve_addr)) {

        Int128 oldv, cmpv, newv;
@@ -271,6 +291,9 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr, 
{

    bool success = false;



    /* We will have raised EXCP_ATOMIC from the translator.  */

    assert(HAVE_CMPXCHG128);



    if (likely(addr == env->reserve_addr)) {

        Int128 oldv, cmpv, newv;

target/ppc/translate.c

+59 −56
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
#include "trace-tcg.h"

#include "exec/translator.h"

#include "exec/log.h"

#include "qemu/atomic128.h"





#define CPU_SINGLE_STEP 0x1
@@ -2654,7 +2655,7 @@ static void gen_lq(DisasContext *ctx) 
    hi = cpu_gpr[rd];



    if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {

#ifdef CONFIG_ATOMIC128

        if (HAVE_ATOMIC128) {

            TCGv_i32 oi = tcg_temp_new_i32();

            if (ctx->le_mode) {

                tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
@@ -2665,11 +2666,11 @@ static void gen_lq(DisasContext *ctx) 
            }

            tcg_temp_free_i32(oi);

            tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));

#else

        } else {

            /* Restart with exclusive lock.  */

            gen_helper_exit_atomic(cpu_env);

            ctx->base.is_jmp = DISAS_NORETURN;

#endif

        }

    } else if (ctx->le_mode) {

        tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ);

        gen_addr_add(ctx, EA, EA, 8);
@@ -2805,7 +2806,7 @@ static void gen_std(DisasContext *ctx) 
        hi = cpu_gpr[rs];



        if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {

#ifdef CONFIG_ATOMIC128

            if (HAVE_ATOMIC128) {

                TCGv_i32 oi = tcg_temp_new_i32();

                if (ctx->le_mode) {

                    tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
@@ -2815,11 +2816,11 @@ static void gen_std(DisasContext *ctx) 
                    gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);

                }

                tcg_temp_free_i32(oi);

#else

            } else {

                /* Restart with exclusive lock.  */

                gen_helper_exit_atomic(cpu_env);

                ctx->base.is_jmp = DISAS_NORETURN;

#endif

            }

        } else if (ctx->le_mode) {

            tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);

            gen_addr_add(ctx, EA, EA, 8);
@@ -3404,7 +3405,7 @@ static void gen_lqarx(DisasContext *ctx) 
    hi = cpu_gpr[rd];



    if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {

#ifdef CONFIG_ATOMIC128

        if (HAVE_ATOMIC128) {

            TCGv_i32 oi = tcg_temp_new_i32();

            if (ctx->le_mode) {

                tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16,
@@ -3417,13 +3418,13 @@ static void gen_lqarx(DisasContext *ctx) 
            }

            tcg_temp_free_i32(oi);

            tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));

#else

        } else {

            /* Restart with exclusive lock.  */

            gen_helper_exit_atomic(cpu_env);

            ctx->base.is_jmp = DISAS_NORETURN;

            tcg_temp_free(EA);

            return;

#endif

        }

    } else if (ctx->le_mode) {

        tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16);

        tcg_gen_mov_tl(cpu_reserve, EA);
@@ -3461,20 +3462,22 @@ static void gen_stqcx_(DisasContext *ctx) 
    hi = cpu_gpr[rs];



    if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {

        if (HAVE_CMPXCHG128) {

            TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);

#ifdef CONFIG_ATOMIC128

            if (ctx->le_mode) {

            gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi);

                gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,

                                             EA, lo, hi, oi);

            } else {

            gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi);

                gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env,

                                             EA, lo, hi, oi);

            }

#else

            tcg_temp_free_i32(oi);

        } else {

            /* Restart with exclusive lock.  */

            gen_helper_exit_atomic(cpu_env);

            ctx->base.is_jmp = DISAS_NORETURN;

#endif

        }

        tcg_temp_free(EA);

        tcg_temp_free_i32(oi);

    } else {

        TCGLabel *lab_fail = gen_new_label();

        TCGLabel *lab_over = gen_new_label();