Commit f23b6bdc authored by Marcel Apfelbaum's avatar Marcel Apfelbaum Committed by Michael S. Tsirkin
Browse files

hw/pcie: implement power controller functionality 



It is needed by hot-unplug in order to get an indication
from the OS when the device can be physically detached.

Signed-off-by: default avatarMarcel Apfelbaum <marcel.a@redhat.com>
Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
parent e4bcd27c

hw/pci-bridge/ioh3420.c

+7 −0
Original line number Diff line number Diff line
@@ -180,6 +180,12 @@ PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction, 
    return PCIE_SLOT(d);

}



static Property ioh3420_props[] = {

    DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,

                    QEMU_PCIE_SLTCAP_PCP_BITNR, true),

    DEFINE_PROP_END_OF_LIST()

};



static const VMStateDescription vmstate_ioh3420 = {

    .name = "ioh-3240-express-root-port",

    .version_id = 1,
@@ -210,6 +216,7 @@ static void ioh3420_class_init(ObjectClass *klass, void *data) 
    dc->desc = "Intel IOH device id 3420 PCIE Root Port";

    dc->reset = ioh3420_reset;

    dc->vmsd = &vmstate_ioh3420;

    dc->props = ioh3420_props;

}



static const TypeInfo ioh3420_info = {

hw/pci-bridge/xio3130_downstream.c

+7 −0
Original line number Diff line number Diff line
@@ -147,6 +147,12 @@ PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction, 
    return PCIE_SLOT(d);

}



static Property xio3130_downstream_props[] = {

    DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,

                    QEMU_PCIE_SLTCAP_PCP_BITNR, true),

    DEFINE_PROP_END_OF_LIST()

};



static const VMStateDescription vmstate_xio3130_downstream = {

    .name = "xio3130-express-downstream-port",

    .version_id = 1,
@@ -177,6 +183,7 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data) 
    dc->desc = "TI X3130 Downstream Port of PCI Express Switch";

    dc->reset = xio3130_downstream_reset;

    dc->vmsd = &vmstate_xio3130_downstream;

    dc->props = xio3130_downstream_props;

}



static const TypeInfo xio3130_downstream_info = {

hw/pci/pcie.c

+32 −1
Original line number Diff line number Diff line
@@ -294,6 +294,15 @@ void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) 
                               PCI_EXP_SLTCAP_AIP |

                               PCI_EXP_SLTCAP_ABP);



    if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {

        pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,

                                   PCI_EXP_SLTCAP_PCP);

        pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,

                                     PCI_EXP_SLTCTL_PCC);

        pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,

                                   PCI_EXP_SLTCTL_PCC);

    }



    pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,

                                 PCI_EXP_SLTCTL_PIC |

                                 PCI_EXP_SLTCTL_AIC);
@@ -327,6 +336,10 @@ void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) 
void pcie_cap_slot_reset(PCIDevice *dev)

{

    uint8_t *exp_cap = dev->config + dev->exp.exp_cap;

    uint8_t port_type = pcie_cap_get_type(dev);



    assert(port_type == PCI_EXP_TYPE_DOWNSTREAM ||

           port_type == PCI_EXP_TYPE_ROOT_PORT);



    PCIE_DEV_PRINTF(dev, "reset\n");
@@ -339,9 +352,27 @@ void pcie_cap_slot_reset(PCIDevice *dev) 
                                 PCI_EXP_SLTCTL_PDCE |

                                 PCI_EXP_SLTCTL_ABPE);

    pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,

                               PCI_EXP_SLTCTL_PIC_OFF |

                               PCI_EXP_SLTCTL_AIC_OFF);



    if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {

        bool populated;

        uint16_t pic;



        /* Downstream ports enforce device number 0. */

        populated = (pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0] != NULL);



        if (populated) {

            pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,

                                         PCI_EXP_SLTCTL_PCC);

        } else {

            pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,

                                       PCI_EXP_SLTCTL_PCC);

        }



        pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF;

        pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic);

     }



    pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,

                                 PCI_EXP_SLTSTA_EIS |/* on reset,

                                                        the lock is released */

include/hw/i386/pc.h

+9 −1
Original line number Diff line number Diff line
@@ -297,6 +297,14 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); 
            .driver   = "ICH9-LPC",\

            .property = "memory-hotplug-support",\

            .value    = "off",\

        },{\

            .driver   = "xio3130-downstream",\

            .property = COMPAT_PROP_PCP,\

            .value    = "off",\

        },{\

            .driver   = "ioh3420",\

            .property = COMPAT_PROP_PCP,\

            .value    = "off",\

        }

 

#define PC_Q35_COMPAT_1_7 \

include/hw/pci/pci.h

+3 −0
Original line number Diff line number Diff line
@@ -158,6 +158,9 @@ enum { 
    QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),

#define QEMU_PCI_SLOTID_BITNR 6

    QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),

    /* PCI Express capability - Power Controller Present */

#define QEMU_PCIE_SLTCAP_PCP_BITNR 7

    QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),

};



#define TYPE_PCI_DEVICE "pci-device"