Commit f22f553e authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20191013' into staging 



Host vector support for tcg/ppc.
Fix thread=single cpu kicking.

# gpg: Signature made Mon 14 Oct 2019 15:11:55 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20191013: (23 commits)
  cpus: kick all vCPUs when running thread=single
  tcg/ppc: Update vector support for v3.00 dup/dupi
  tcg/ppc: Update vector support for v3.00 load/store
  tcg/ppc: Update vector support for v3.00 Altivec
  tcg/ppc: Update vector support for v2.07 FP
  tcg/ppc: Update vector support for v2.07 VSX
  tcg/ppc: Update vector support for v2.07 Altivec
  tcg/ppc: Update vector support for VSX
  tcg/ppc: Enable Altivec detection
  tcg/ppc: Support vector dup2
  tcg/ppc: Support vector multiply
  tcg/ppc: Support vector shift by immediate
  tcg/ppc: Add support for vector saturated add/subtract
  tcg/ppc: Add support for vector add/subtract
  tcg/ppc: Add support for vector maximum/minimum
  tcg/ppc: Add support for load/store/logic/comparison
  tcg/ppc: Enable tcg backend vector compilation
  tcg/ppc: Replace HAVE_ISEL macro with a variable
  tcg/ppc: Replace HAVE_ISA_2_06
  tcg/ppc: Create TCGPowerISA and have_isa
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 39b68bc4 e8f22f76

cpus.c

+18 −6
Original line number Diff line number Diff line
@@ -949,8 +949,8 @@ static inline int64_t qemu_tcg_next_kick(void) 
    return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD;

}



/* Kick the currently round-robin scheduled vCPU */

static void qemu_cpu_kick_rr_cpu(void)

/* Kick the currently round-robin scheduled vCPU to next */

static void qemu_cpu_kick_rr_next_cpu(void)

{

    CPUState *cpu;

    do {
@@ -961,6 +961,16 @@ static void qemu_cpu_kick_rr_cpu(void) 
    } while (cpu != atomic_mb_read(&tcg_current_rr_cpu));

}



/* Kick all RR vCPUs */

static void qemu_cpu_kick_rr_cpus(void)

{

    CPUState *cpu;



    CPU_FOREACH(cpu) {

        cpu_exit(cpu);

    };

}



static void do_nothing(CPUState *cpu, run_on_cpu_data unused)

{

}
@@ -993,7 +1003,7 @@ void qemu_timer_notify_cb(void *opaque, QEMUClockType type) 
static void kick_tcg_thread(void *opaque)

{

    timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());

    qemu_cpu_kick_rr_cpu();

    qemu_cpu_kick_rr_next_cpu();

}



static void start_tcg_kick_timer(void)
@@ -1827,9 +1837,11 @@ void qemu_cpu_kick(CPUState *cpu) 
{

    qemu_cond_broadcast(cpu->halt_cond);

    if (tcg_enabled()) {

        if (qemu_tcg_mttcg_enabled()) {

            cpu_exit(cpu);

        /* NOP unless doing single-thread RR */

        qemu_cpu_kick_rr_cpu();

        } else {

            qemu_cpu_kick_rr_cpus();

        }

    } else {

        if (hax_enabled()) {

            /*

tcg/ppc/tcg-target.h

+48 −3
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ 
# define TCG_TARGET_REG_BITS  32

#endif



#define TCG_TARGET_NB_REGS 32

#define TCG_TARGET_NB_REGS 64

#define TCG_TARGET_INSN_UNIT_SIZE 4

#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
@@ -45,12 +45,33 @@ typedef enum { 
    TCG_REG_R24, TCG_REG_R25, TCG_REG_R26, TCG_REG_R27,

    TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31,



    TCG_REG_V0,  TCG_REG_V1,  TCG_REG_V2,  TCG_REG_V3,

    TCG_REG_V4,  TCG_REG_V5,  TCG_REG_V6,  TCG_REG_V7,

    TCG_REG_V8,  TCG_REG_V9,  TCG_REG_V10, TCG_REG_V11,

    TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,

    TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,

    TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,

    TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,

    TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,



    TCG_REG_CALL_STACK = TCG_REG_R1,

    TCG_AREG0 = TCG_REG_R27

} TCGReg;



extern bool have_isa_2_06;

extern bool have_isa_3_00;

typedef enum {

    tcg_isa_base,

    tcg_isa_2_06,

    tcg_isa_2_07,

    tcg_isa_3_00,

} TCGPowerISA;



extern TCGPowerISA have_isa;

extern bool have_altivec;

extern bool have_vsx;



#define have_isa_2_06  (have_isa >= tcg_isa_2_06)

#define have_isa_2_07  (have_isa >= tcg_isa_2_07)

#define have_isa_3_00  (have_isa >= tcg_isa_3_00)



/* optional instructions automatically implemented */

#define TCG_TARGET_HAS_ext8u_i32        0 /* andi */
@@ -126,6 +147,30 @@ extern bool have_isa_3_00; 
#define TCG_TARGET_HAS_mulsh_i64        1

#endif



/*

 * While technically Altivec could support V64, it has no 64-bit store

 * instruction and substituting two 32-bit stores makes the generated

 * code quite large.

 */

#define TCG_TARGET_HAS_v64              have_vsx

#define TCG_TARGET_HAS_v128             have_altivec

#define TCG_TARGET_HAS_v256             0



#define TCG_TARGET_HAS_andc_vec         1

#define TCG_TARGET_HAS_orc_vec          have_isa_2_07

#define TCG_TARGET_HAS_not_vec          1

#define TCG_TARGET_HAS_neg_vec          have_isa_3_00

#define TCG_TARGET_HAS_abs_vec          0

#define TCG_TARGET_HAS_shi_vec          0

#define TCG_TARGET_HAS_shs_vec          0

#define TCG_TARGET_HAS_shv_vec          1

#define TCG_TARGET_HAS_cmp_vec          1

#define TCG_TARGET_HAS_mul_vec          1

#define TCG_TARGET_HAS_sat_vec          1

#define TCG_TARGET_HAS_minmax_vec       1

#define TCG_TARGET_HAS_bitsel_vec       have_vsx

#define TCG_TARGET_HAS_cmpsel_vec       0



void flush_icache_range(uintptr_t start, uintptr_t stop);

void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);

tcg/ppc/tcg-target.inc.c

+1038 −76

File changed.

Preview size limit exceeded, changes collapsed.

tcg/ppc/tcg-target.opc.h

0 → 100644
+13 −0
Original line number Diff line number Diff line 
/*

 * Target-specific opcodes for host vector expansion.  These will be

 * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,

 * consider these to be UNSPEC with names.

 */



DEF(ppc_mrgh_vec, 1, 2, 0, IMPLVEC)

DEF(ppc_mrgl_vec, 1, 2, 0, IMPLVEC)

DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC)

DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC)

DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC)

DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC)

DEF(ppc_rotl_vec, 1, 2, 0, IMPLVEC)