Commit f076803b authored by Laurent Vivier's avatar Laurent Vivier
Browse files

target-m68k: define m680x0 CPUs and features 



This patch defines height new features:

    - M68K_FEATURE_SCALED_INDEX, scaled address index register
    - M68K_FEATURE_LONG_MULDIV, 32bit multiply/divide
    - M68K_FEATURE_QUAD_MULDIV, 64bit multiply/divide
    - M68K_FEATURE_BCCL, long conditional branches
    - M68K_FEATURE_BITFIELD, bit field instructions
    - M68K_FEATURE_FPU, FPU instructions
    - M68K_FEATURE_CAS, cas instruction
    - M68K_FEATURE_BKPT, bkpt instruction

Original patch from Andreas Schwab <schwab@linux-m68k.org>
Signed-off-by: default avatarLaurent Vivier <laurent@vivier.eu>
parent b2085257

target-m68k/cpu.c

+56 −0
Original line number Diff line number Diff line
@@ -98,6 +98,57 @@ static void m5206_cpu_initfn(Object *obj) 
    m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);

}



static void m68000_cpu_initfn(Object *obj)

{

    M68kCPU *cpu = M68K_CPU(obj);

    CPUM68KState *env = &cpu->env;



    m68k_set_feature(env, M68K_FEATURE_M68000);

    m68k_set_feature(env, M68K_FEATURE_USP);

    m68k_set_feature(env, M68K_FEATURE_WORD_INDEX);

}



static void m68020_cpu_initfn(Object *obj)

{

    M68kCPU *cpu = M68K_CPU(obj);

    CPUM68KState *env = &cpu->env;



    m68k_set_feature(env, M68K_FEATURE_M68000);

    m68k_set_feature(env, M68K_FEATURE_USP);

    m68k_set_feature(env, M68K_FEATURE_WORD_INDEX);

    m68k_set_feature(env, M68K_FEATURE_QUAD_MULDIV);

    m68k_set_feature(env, M68K_FEATURE_BRAL);

    m68k_set_feature(env, M68K_FEATURE_BCCL);

    m68k_set_feature(env, M68K_FEATURE_BITFIELD);

    m68k_set_feature(env, M68K_FEATURE_EXT_FULL);

    m68k_set_feature(env, M68K_FEATURE_SCALED_INDEX);

    m68k_set_feature(env, M68K_FEATURE_LONG_MULDIV);

    m68k_set_feature(env, M68K_FEATURE_FPU);

    m68k_set_feature(env, M68K_FEATURE_CAS);

    m68k_set_feature(env, M68K_FEATURE_BKPT);

}

#define m68030_cpu_initfn m68020_cpu_initfn

#define m68040_cpu_initfn m68020_cpu_initfn



static void m68060_cpu_initfn(Object *obj)

{

    M68kCPU *cpu = M68K_CPU(obj);

    CPUM68KState *env = &cpu->env;



    m68k_set_feature(env, M68K_FEATURE_M68000);

    m68k_set_feature(env, M68K_FEATURE_USP);

    m68k_set_feature(env, M68K_FEATURE_WORD_INDEX);

    m68k_set_feature(env, M68K_FEATURE_BRAL);

    m68k_set_feature(env, M68K_FEATURE_BCCL);

    m68k_set_feature(env, M68K_FEATURE_BITFIELD);

    m68k_set_feature(env, M68K_FEATURE_EXT_FULL);

    m68k_set_feature(env, M68K_FEATURE_SCALED_INDEX);

    m68k_set_feature(env, M68K_FEATURE_LONG_MULDIV);

    m68k_set_feature(env, M68K_FEATURE_FPU);

    m68k_set_feature(env, M68K_FEATURE_CAS);

    m68k_set_feature(env, M68K_FEATURE_BKPT);

}



static void m5208_cpu_initfn(Object *obj)

{

    M68kCPU *cpu = M68K_CPU(obj);
@@ -148,6 +199,11 @@ typedef struct M68kCPUInfo { 
} M68kCPUInfo;



static const M68kCPUInfo m68k_cpus[] = {

    { .name = "m68000", .instance_init = m68000_cpu_initfn },

    { .name = "m68020", .instance_init = m68020_cpu_initfn },

    { .name = "m68030", .instance_init = m68030_cpu_initfn },

    { .name = "m68040", .instance_init = m68040_cpu_initfn },

    { .name = "m68060", .instance_init = m68060_cpu_initfn },

    { .name = "m5206", .instance_init = m5206_cpu_initfn },

    { .name = "m5208", .instance_init = m5208_cpu_initfn },

    { .name = "cfv4e", .instance_init = cfv4e_cpu_initfn },

target-m68k/cpu.h

+10 −1
Original line number Diff line number Diff line
@@ -215,6 +215,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr); 
   ISA revisions mentioned.  */



enum m68k_features {

    M68K_FEATURE_M68000,

    M68K_FEATURE_CF_ISA_A,

    M68K_FEATURE_CF_ISA_B, /* (ISA B or C).  */

    M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).  */
@@ -225,7 +226,15 @@ enum m68k_features { 
    M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate).  */

    M68K_FEATURE_USP, /* User Stack Pointer.  (ISA A+, B or C).  */

    M68K_FEATURE_EXT_FULL, /* 68020+ full extension word.  */

    M68K_FEATURE_WORD_INDEX /* word sized address index registers.  */

    M68K_FEATURE_WORD_INDEX, /* word sized address index registers.  */

    M68K_FEATURE_SCALED_INDEX, /* scaled address index registers.  */

    M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */

    M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */

    M68K_FEATURE_BCCL, /* Long conditional branches.  */

    M68K_FEATURE_BITFIELD, /* Bit field insns.  */

    M68K_FEATURE_FPU,

    M68K_FEATURE_CAS,

    M68K_FEATURE_BKPT,

};



static inline int m68k_feature(CPUM68KState *env, int feature)

target-m68k/translate.c

+76 −44
Original line number Diff line number Diff line
@@ -2846,90 +2846,118 @@ void register_m68k_insns (CPUM68KState *env) 
    if (opcode_table[0] != NULL) {

        return;

    }



    /* use BASE() for instruction available

     * for CF_ISA_A and M68000.

     */

#define BASE(name, opcode, mask) \

    register_opcode(disas_##name, 0x##opcode, 0x##mask)

#define INSN(name, opcode, mask, feature) do { \

    if (m68k_feature(env, M68K_FEATURE_##feature)) \

        register_opcode(disas_##name, 0x##opcode, 0x##mask); \

        BASE(name, opcode, mask); \

    } while(0)

    INSN(undef,     0000, 0000, CF_ISA_A);

    BASE(undef,     0000, 0000);

    INSN(arith_im,  0080, fff8, CF_ISA_A);

    INSN(arith_im,  0000, ff00, M68000);

    INSN(undef,     00c0, ffc0, M68000);

    INSN(bitrev,    00c0, fff8, CF_ISA_APLUSC);

    INSN(bitop_reg, 0100, f1c0, CF_ISA_A);

    INSN(bitop_reg, 0140, f1c0, CF_ISA_A);

    INSN(bitop_reg, 0180, f1c0, CF_ISA_A);

    INSN(bitop_reg, 01c0, f1c0, CF_ISA_A);

    BASE(bitop_reg, 0100, f1c0);

    BASE(bitop_reg, 0140, f1c0);

    BASE(bitop_reg, 0180, f1c0);

    BASE(bitop_reg, 01c0, f1c0);

    INSN(arith_im,  0280, fff8, CF_ISA_A);

    INSN(arith_im,  0200, ff00, M68000);

    INSN(undef,     02c0, ffc0, M68000);

    INSN(byterev,   02c0, fff8, CF_ISA_APLUSC);

    INSN(arith_im,  0480, fff8, CF_ISA_A);

    INSN(arith_im,  0400, ff00, M68000);

    INSN(undef,     04c0, ffc0, M68000);

    INSN(arith_im,  0600, ff00, M68000);

    INSN(undef,     06c0, ffc0, M68000);

    INSN(ff1,       04c0, fff8, CF_ISA_APLUSC);

    INSN(arith_im,  0680, fff8, CF_ISA_A);

    INSN(bitop_im,  0800, ffc0, CF_ISA_A);

    INSN(bitop_im,  0840, ffc0, CF_ISA_A);

    INSN(bitop_im,  0880, ffc0, CF_ISA_A);

    INSN(bitop_im,  08c0, ffc0, CF_ISA_A);

    INSN(arith_im,  0a80, fff8, CF_ISA_A);

    INSN(arith_im,  0c00, ff38, CF_ISA_A);

    INSN(move,      1000, f000, CF_ISA_A);

    INSN(move,      2000, f000, CF_ISA_A);

    INSN(move,      3000, f000, CF_ISA_A);

    INSN(arith_im,  0c00, ff00, M68000);

    BASE(bitop_im,  0800, ffc0);

    BASE(bitop_im,  0840, ffc0);

    BASE(bitop_im,  0880, ffc0);

    BASE(bitop_im,  08c0, ffc0);

    INSN(arith_im,  0a80, fff8, CF_ISA_A);

    INSN(arith_im,  0a00, ff00, M68000);

    BASE(move,      1000, f000);

    BASE(move,      2000, f000);

    BASE(move,      3000, f000);

    INSN(strldsr,   40e7, ffff, CF_ISA_APLUSC);

    INSN(negx,      4080, fff8, CF_ISA_A);

    INSN(move_from_sr, 40c0, fff8, CF_ISA_A);

    INSN(lea,       41c0, f1c0, CF_ISA_A);

    INSN(clr,       4200, ff00, CF_ISA_A);

    INSN(undef,     42c0, ffc0, CF_ISA_A);

    INSN(move_from_sr, 40c0, ffc0, M68000);

    BASE(lea,       41c0, f1c0);

    BASE(clr,       4200, ff00);

    BASE(undef,     42c0, ffc0);

    INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);

    INSN(neg,       4480, fff8, CF_ISA_A);

    INSN(move_to_ccr, 44c0, ffc0, CF_ISA_A);

    INSN(neg,       4400, ff00, M68000);

    INSN(undef,     44c0, ffc0, M68000);

    BASE(move_to_ccr, 44c0, ffc0);

    INSN(not,       4680, fff8, CF_ISA_A);

    INSN(not,       4600, ff00, M68000);

    INSN(undef,     46c0, ffc0, M68000);

    INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);

    INSN(pea,       4840, ffc0, CF_ISA_A);

    INSN(swap,      4840, fff8, CF_ISA_A);

    INSN(movem,     48c0, fbc0, CF_ISA_A);

    INSN(ext,       4880, fff8, CF_ISA_A);

    INSN(ext,       48c0, fff8, CF_ISA_A);

    INSN(ext,       49c0, fff8, CF_ISA_A);

    INSN(tst,       4a00, ff00, CF_ISA_A);

    BASE(pea,       4840, ffc0);

    BASE(swap,      4840, fff8);

    BASE(movem,     48c0, fbc0);

    BASE(ext,       4880, fff8);

    BASE(ext,       48c0, fff8);

    BASE(ext,       49c0, fff8);

    BASE(tst,       4a00, ff00);

    INSN(tas,       4ac0, ffc0, CF_ISA_B);

    INSN(tas,       4ac0, ffc0, M68000);

    INSN(halt,      4ac8, ffff, CF_ISA_A);

    INSN(pulse,     4acc, ffff, CF_ISA_A);

    INSN(illegal,   4afc, ffff, CF_ISA_A);

    BASE(illegal,   4afc, ffff);

    INSN(mull,      4c00, ffc0, CF_ISA_A);

    INSN(mull,      4c00, ffc0, LONG_MULDIV);

    INSN(divl,      4c40, ffc0, CF_ISA_A);

    INSN(divl,      4c40, ffc0, LONG_MULDIV);

    INSN(sats,      4c80, fff8, CF_ISA_B);

    INSN(trap,      4e40, fff0, CF_ISA_A);

    INSN(link,      4e50, fff8, CF_ISA_A);

    INSN(unlk,      4e58, fff8, CF_ISA_A);

    BASE(trap,      4e40, fff0);

    BASE(link,      4e50, fff8);

    BASE(unlk,      4e58, fff8);

    INSN(move_to_usp, 4e60, fff8, USP);

    INSN(move_from_usp, 4e68, fff8, USP);

    INSN(nop,       4e71, ffff, CF_ISA_A);

    INSN(stop,      4e72, ffff, CF_ISA_A);

    INSN(rte,       4e73, ffff, CF_ISA_A);

    INSN(rts,       4e75, ffff, CF_ISA_A);

    BASE(nop,       4e71, ffff);

    BASE(stop,      4e72, ffff);

    BASE(rte,       4e73, ffff);

    BASE(rts,       4e75, ffff);

    INSN(movec,     4e7b, ffff, CF_ISA_A);

    INSN(jump,      4e80, ffc0, CF_ISA_A);

    BASE(jump,      4e80, ffc0);

    INSN(jump,      4ec0, ffc0, CF_ISA_A);

    INSN(addsubq,   5180, f1c0, CF_ISA_A);

    INSN(jump,      4ec0, ffc0, M68000);

    INSN(addsubq,   5000, f080, M68000);

    INSN(addsubq,   5080, f0c0, M68000);

    INSN(scc,       50c0, f0f8, CF_ISA_A);

    INSN(addsubq,   5080, f1c0, CF_ISA_A);

    INSN(tpf,       51f8, fff8, CF_ISA_A);



    /* Branch instructions.  */

    INSN(branch,    6000, f000, CF_ISA_A);

    BASE(branch,    6000, f000);

    /* Disable long branch instructions, then add back the ones we want.  */

    INSN(undef,     60ff, f0ff, CF_ISA_A); /* All long branches.  */

    BASE(undef,     60ff, f0ff); /* All long branches.  */

    INSN(branch,    60ff, f0ff, CF_ISA_B);

    INSN(undef,     60ff, ffff, CF_ISA_B); /* bra.l */

    INSN(branch,    60ff, ffff, BRAL);

    INSN(branch,    60ff, f0ff, BCCL);



    INSN(moveq,     7000, f100, CF_ISA_A);

    BASE(moveq,     7000, f100);

    INSN(mvzs,      7100, f100, CF_ISA_B);

    INSN(or,        8000, f000, CF_ISA_A);

    INSN(divw,      80c0, f0c0, CF_ISA_A);

    INSN(addsub,    9000, f000, CF_ISA_A);

    BASE(or,        8000, f000);

    BASE(divw,      80c0, f0c0);

    BASE(addsub,    9000, f000);

    INSN(subx,      9180, f1f8, CF_ISA_A);

    INSN(suba,      91c0, f1c0, CF_ISA_A);



    INSN(undef_mac, a000, f000, CF_ISA_A);

    BASE(undef_mac, a000, f000);

    INSN(mac,       a000, f100, CF_EMAC);

    INSN(from_mac,  a180, f9b0, CF_EMAC);

    INSN(move_mac,  a110, f9fc, CF_EMAC);
@@ -2948,12 +2976,16 @@ void register_m68k_insns (CPUM68KState *env) 
    INSN(cmpa,      b0c0, f1c0, CF_ISA_B); /* cmpa.w */

    INSN(cmp,       b080, f1c0, CF_ISA_A);

    INSN(cmpa,      b1c0, f1c0, CF_ISA_A);

    INSN(cmp,       b000, f100, M68000);

    INSN(eor,       b100, f100, M68000);

    INSN(cmpa,      b0c0, f0c0, M68000);

    INSN(eor,       b180, f1c0, CF_ISA_A);

    INSN(and,       c000, f000, CF_ISA_A);

    INSN(mulw,      c0c0, f0c0, CF_ISA_A);

    INSN(addsub,    d000, f000, CF_ISA_A);

    BASE(and,       c000, f000);

    BASE(mulw,      c0c0, f0c0);

    BASE(addsub,    d000, f000);

    INSN(addx,      d180, f1f8, CF_ISA_A);

    INSN(adda,      d1c0, f1c0, CF_ISA_A);

    INSN(adda,      d0c0, f0c0, M68000);

    INSN(shift_im,  e080, f0f0, CF_ISA_A);

    INSN(shift_reg, e0a0, f0f0, CF_ISA_A);

    INSN(undef_fpu, f000, f000, CF_ISA_A);