Commit f073cd3a authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170207-1' into staging 



target-arm:
 * new "unimplemented" device for stubbing out devices in a
   system model so accesses can be logged
 * stellaris: document the SoC memory map
 * arm: create instruction syndromes for AArch32 data aborts
 * arm: Correctly handle watchpoints for BE32 CPUs
 * Fix Thumb-1 BE32 execution and disassembly
 * arm: Add cfgend parameter for ARM CPU selection
 * sd: sdhci: check data length during dma_memory_read
 * aspeed: add a watchdog controller
 * integratorcp: adding vmstate for save/restore

# gpg: Signature made Tue 07 Feb 2017 19:20:19 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170207-1:
  stellaris: Use the 'unimplemented' device for parts we don't implement
  hw/misc: New "unimplemented" sysbus device
  stellaris: Document memory map and which SoC devices are unimplemented
  target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
  target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
  arm: Correctly handle watchpoints for BE32 CPUs
  Fix Thumb-1 BE32 execution and disassembly.
  target/arm: Add cfgend parameter for ARM CPU selection.
  hw/arm/integratorcp: Support specifying features via -cpu
  sd: sdhci: check data length during dma_memory_read
  aspeed: add a watchdog controller
  wdt: Add Aspeed watchdog device model
  integratorcp: adding vmstate for save/restore

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents d0dff238 aecfbbc9

disas.c

+1 −0
Original line number Diff line number Diff line
@@ -190,6 +190,7 @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code, 


    s.cpu = cpu;

    s.info.read_memory_func = target_read_memory;

    s.info.read_memory_inner_func = NULL;

    s.info.buffer_vma = code;

    s.info.buffer_length = size;

    s.info.print_address_func = generic_print_address;

exec.c

+1 −0
Original line number Diff line number Diff line
@@ -2115,6 +2115,7 @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags) 
        return;

    }

    vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;

    vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);

    QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {

        if (cpu_watchpoint_address_matches(wp, vaddr, len)

            && (wp->flags & flags)) {

hw/arm/aspeed_soc.c

+13 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#define ASPEED_SOC_SCU_BASE         0x1E6E2000

#define ASPEED_SOC_SRAM_BASE        0x1E720000

#define ASPEED_SOC_TIMER_BASE       0x1E782000

#define ASPEED_SOC_WDT_BASE         0x1E785000

#define ASPEED_SOC_I2C_BASE         0x1E78A000



static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
@@ -170,6 +171,10 @@ static void aspeed_soc_init(Object *obj) 
                         sc->info->silicon_rev);

    object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),

                              "ram-size", &error_abort);



    object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);

    object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);

    qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());

}



static void aspeed_soc_realize(DeviceState *dev, Error **errp)
@@ -286,6 +291,14 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) 
        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);



    /* Watch dog */

    object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);

}



static void aspeed_soc_class_init(ObjectClass *oc, void *data)

hw/arm/integratorcp.c

+76 −2
Original line number Diff line number Diff line
@@ -53,6 +53,26 @@ static uint8_t integrator_spd[128] = { 
   0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40

};



static const VMStateDescription vmstate_integratorcm = {

    .name = "integratorcm",

    .version_id = 1,

    .minimum_version_id = 1,

    .fields      = (VMStateField[]) {

        VMSTATE_UINT32(cm_osc, IntegratorCMState),

        VMSTATE_UINT32(cm_ctrl, IntegratorCMState),

        VMSTATE_UINT32(cm_lock, IntegratorCMState),

        VMSTATE_UINT32(cm_auxosc, IntegratorCMState),

        VMSTATE_UINT32(cm_sdram, IntegratorCMState),

        VMSTATE_UINT32(cm_init, IntegratorCMState),

        VMSTATE_UINT32(cm_flags, IntegratorCMState),

        VMSTATE_UINT32(cm_nvflags, IntegratorCMState),

        VMSTATE_UINT32(int_level, IntegratorCMState),

        VMSTATE_UINT32(irq_enabled, IntegratorCMState),

        VMSTATE_UINT32(fiq_enabled, IntegratorCMState),

        VMSTATE_END_OF_LIST()

    }

};



static uint64_t integratorcm_read(void *opaque, hwaddr offset,

                                  unsigned size)

{
@@ -309,6 +329,18 @@ typedef struct icp_pic_state { 
    qemu_irq parent_fiq;

} icp_pic_state;



static const VMStateDescription vmstate_icp_pic = {

    .name = "icp_pic",

    .version_id = 1,

    .minimum_version_id = 1,

    .fields      = (VMStateField[]) {

        VMSTATE_UINT32(level, icp_pic_state),

        VMSTATE_UINT32(irq_enabled, icp_pic_state),

        VMSTATE_UINT32(fiq_enabled, icp_pic_state),

        VMSTATE_END_OF_LIST()

    }

};



static void icp_pic_update(icp_pic_state *s)

{

    uint32_t flags;
@@ -438,6 +470,16 @@ typedef struct ICPCtrlRegsState { 
#define ICP_INTREG_WPROT        (1 << 0)

#define ICP_INTREG_CARDIN       (1 << 3)



static const VMStateDescription vmstate_icp_control = {

    .name = "icp_control",

    .version_id = 1,

    .minimum_version_id = 1,

    .fields      = (VMStateField[]) {

        VMSTATE_UINT32(intreg_state, ICPCtrlRegsState),

        VMSTATE_END_OF_LIST()

    }

};



static uint64_t icp_control_read(void *opaque, hwaddr offset,

                                 unsigned size)

{
@@ -535,27 +577,42 @@ static void integratorcp_init(MachineState *machine) 
    const char *kernel_filename = machine->kernel_filename;

    const char *kernel_cmdline = machine->kernel_cmdline;

    const char *initrd_filename = machine->initrd_filename;

    char **cpustr;

    ObjectClass *cpu_oc;

    CPUClass *cc;

    Object *cpuobj;

    ARMCPU *cpu;

    const char *typename;

    MemoryRegion *address_space_mem = get_system_memory();

    MemoryRegion *ram = g_new(MemoryRegion, 1);

    MemoryRegion *ram_alias = g_new(MemoryRegion, 1);

    qemu_irq pic[32];

    DeviceState *dev, *sic, *icp;

    int i;

    Error *err = NULL;



    if (!cpu_model) {

        cpu_model = "arm926";

    }



    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);

    cpustr = g_strsplit(cpu_model, ",", 2);



    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);

    if (!cpu_oc) {

        fprintf(stderr, "Unable to find CPU definition\n");

        exit(1);

    }

    typename = object_class_get_name(cpu_oc);



    cpuobj = object_new(object_class_get_name(cpu_oc));

    cc = CPU_CLASS(cpu_oc);

    cc->parse_features(typename, cpustr[1], &err);

    g_strfreev(cpustr);

    if (err) {

        error_report_err(err);

        exit(1);

    }



    cpuobj = object_new(typename);



    /* By default ARM1176 CPUs have EL3 enabled.  This board does not

     * currently support EL3 so the CPU EL3 property is disabled before
@@ -640,6 +697,21 @@ static void core_class_init(ObjectClass *klass, void *data) 


    dc->props = core_properties;

    dc->realize = integratorcm_realize;

    dc->vmsd = &vmstate_integratorcm;

}



static void icp_pic_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);



    dc->vmsd = &vmstate_icp_pic;

}



static void icp_control_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);



    dc->vmsd = &vmstate_icp_control;

}



static const TypeInfo core_info = {
@@ -655,6 +727,7 @@ static const TypeInfo icp_pic_info = { 
    .parent        = TYPE_SYS_BUS_DEVICE,

    .instance_size = sizeof(icp_pic_state),

    .instance_init = icp_pic_init,

    .class_init    = icp_pic_class_init,

};



static const TypeInfo icp_ctrl_regs_info = {
@@ -662,6 +735,7 @@ static const TypeInfo icp_ctrl_regs_info = { 
    .parent        = TYPE_SYS_BUS_DEVICE,

    .instance_size = sizeof(ICPCtrlRegsState),

    .instance_init = icp_control_init,

    .class_init    = icp_control_class_init,

};



static void integratorcp_register_types(void)

hw/arm/stellaris.c

+48 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include "exec/address-spaces.h"

#include "sysemu/sysemu.h"

#include "hw/char/pl011.h"

#include "hw/misc/unimp.h"



#define GPIO_A 0

#define GPIO_B 1
@@ -1220,6 +1221,40 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, 
        0x40024000, 0x40025000, 0x40026000};

    static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};



    /* Memory map of SoC devices, from

     * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)

     * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf

     *

     * 40000000 wdtimer (unimplemented)

     * 40002000 i2c (unimplemented)

     * 40004000 GPIO

     * 40005000 GPIO

     * 40006000 GPIO

     * 40007000 GPIO

     * 40008000 SSI

     * 4000c000 UART

     * 4000d000 UART

     * 4000e000 UART

     * 40020000 i2c

     * 40021000 i2c (unimplemented)

     * 40024000 GPIO

     * 40025000 GPIO

     * 40026000 GPIO

     * 40028000 PWM (unimplemented)

     * 4002c000 QEI (unimplemented)

     * 4002d000 QEI (unimplemented)

     * 40030000 gptimer

     * 40031000 gptimer

     * 40032000 gptimer

     * 40033000 gptimer

     * 40038000 ADC

     * 4003c000 analogue comparator (unimplemented)

     * 40048000 ethernet

     * 400fc000 hibernation module (unimplemented)

     * 400fd000 flash memory control (unimplemented)

     * 400fe000 system control

     */



    DeviceState *gpio_dev[7], *nvic;

    qemu_irq gpio_in[7][8];

    qemu_irq gpio_out[7][8];
@@ -1370,6 +1405,19 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, 
            }

        }

    }



    /* Add dummy regions for the devices we don't implement yet,

     * so guest accesses don't cause unlogged crashes.

     */

    create_unimplemented_device("wdtimer", 0x40000000, 0x1000);

    create_unimplemented_device("i2c-0", 0x40002000, 0x1000);

    create_unimplemented_device("i2c-2", 0x40021000, 0x1000);

    create_unimplemented_device("PWM", 0x40028000, 0x1000);

    create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);

    create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);

    create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);

    create_unimplemented_device("hibernation", 0x400fc000, 0x1000);

    create_unimplemented_device("flash-control", 0x400fd000, 0x1000);

}



/* FIXME: Figure out how to generate these from stellaris_boards.  */