Commit ee70fc26 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-24-2019-v2' into staging 



MIPS queue for October 24th, 2019 - v2

# gpg: Signature made Fri 25 Oct 2019 17:37:29 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-oct-24-2019-v2:
  tests/ssh_linux_malta: Fix 64-bit target tests
  tests/ssh_linux_malta: Refactor how to get image/kernel info
  tests/ssh_linux_malta: Match stricter console output
  tests/ssh_linux_malta: Remove duplicated test
  tests/ssh_linux_malta: Run tests using a snapshot image
  target/mips: Refactor handling of vector compare 'less than' (signed) instructions
  target/mips: Refactor handling of vector compare 'equal' instructions
  target/mips: Demacro LMI decoder
  target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D>
  target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D>
  target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D>
  target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D>
  target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D>
  target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D>
  target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D>
  target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D>
  target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D>
  MAINTAINERS: Update mail address of Aleksandar Rikalo
  target/mips: Clean up op_helper.c
  target/mips: Clean up helper.c

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 03bf012e 220ad858

.mailmap

+3 −2
Original line number Diff line number Diff line
@@ -39,10 +39,11 @@ Julia Suvorova <jusual@mail.ru> Julia Suvorova via Qemu-devel <qemu-devel@nongnu 
Justin Terry (VM) <juterry@microsoft.com> Justin Terry (VM) via Qemu-devel <qemu-devel@nongnu.org>



# Next, replace old addresses by a more recent one.

Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>

James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>

Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@mips.com>

Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@imgtec.com>

Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> <arikalo@wavecomp.com>

Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>

James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>

Paul Burton <pburton@wavecomp.com> <paul.burton@mips.com>

Paul Burton <pburton@wavecomp.com> <paul.burton@imgtec.com>

Paul Burton <pburton@wavecomp.com> <paul@archlinuxmips.org>

MAINTAINERS

+9 −9
Original line number Diff line number Diff line
@@ -208,7 +208,7 @@ F: disas/microblaze.c 
MIPS TCG CPUs

M: Aurelien Jarno <aurelien@aurel32.net>

M: Aleksandar Markovic <amarkovic@wavecomp.com>

R: Aleksandar Rikalo <arikalo@wavecomp.com>

R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>

S: Maintained

F: target/mips/

F: default-configs/*mips*
@@ -363,7 +363,7 @@ F: target/arm/kvm.c 


MIPS KVM CPUs

M: James Hogan <jhogan@kernel.org>

R: Aleksandar Rikalo <arikalo@wavecomp.com>

R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>

S: Maintained

F: target/mips/kvm.c
@@ -934,7 +934,7 @@ MIPS Machines 
-------------

Jazz

M: Hervé Poussineau <hpoussin@reactos.org>

R: Aleksandar Rikalo <arikalo@wavecomp.com>

R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>

S: Maintained

F: hw/mips/mips_jazz.c

F: hw/display/jazz_led.c
@@ -942,7 +942,7 @@ F: hw/dma/rc4030.c 


Malta

M: Aurelien Jarno <aurelien@aurel32.net>

R: Aleksandar Rikalo <arikalo@wavecomp.com>

R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>

S: Maintained

F: hw/mips/mips_malta.c

F: hw/mips/gt64xxx_pci.c
@@ -950,20 +950,20 @@ F: tests/acceptance/linux_ssh_mips_malta.py 


Mipssim

M: Aleksandar Markovic <amarkovic@wavecomp.com>

R: Aleksandar Rikalo <arikalo@wavecomp.com>

R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>

S: Odd Fixes

F: hw/mips/mips_mipssim.c

F: hw/net/mipsnet.c



R4000

M: Aurelien Jarno <aurelien@aurel32.net>

R: Aleksandar Rikalo <arikalo@wavecomp.com>

R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>

S: Maintained

F: hw/mips/mips_r4k.c



Fulong 2E

M: Aleksandar Markovic <amarkovic@wavecomp.com>

R: Aleksandar Rikalo <arikalo@wavecomp.com>

R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>

S: Odd Fixes

F: hw/mips/mips_fulong2e.c

F: hw/isa/vt82c686.c
@@ -972,7 +972,7 @@ F: include/hw/isa/vt82c686.h 


Boston

M: Paul Burton <pburton@wavecomp.com>

R: Aleksandar Rikalo <arikalo@wavecomp.com>

R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>

S: Maintained

F: hw/core/loader-fit.c

F: hw/mips/boston.c
@@ -2352,7 +2352,7 @@ F: disas/i386.c 


MIPS TCG target

M: Aurelien Jarno <aurelien@aurel32.net>

R: Aleksandar Rikalo <arikalo@wavecomp.com>

R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>

S: Maintained

F: tcg/mips/

target/mips/helper.c

+74 −49
Original line number Diff line number Diff line
@@ -52,14 +52,16 @@ int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, 
                          target_ulong address, int rw, int access_type)

{

    if (address <= (int32_t)0x7FFFFFFFUL) {

        if (!(env->CP0_Status & (1 << CP0St_ERL)))

        if (!(env->CP0_Status & (1 << CP0St_ERL))) {

            *physical = address + 0x40000000UL;

        else

        } else {

            *physical = address;

    } else if (address <= (int32_t)0xBFFFFFFFUL)

        }

    } else if (address <= (int32_t)0xBFFFFFFFUL) {

        *physical = address & 0x1FFFFFFF;

    else

    } else {

        *physical = address;

    }



    *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;

    return TLBRET_MATCH;
@@ -99,8 +101,9 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, 
            if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {

                *physical = tlb->PFN[n] | (address & (mask >> 1));

                *prot = PAGE_READ;

                if (n ? tlb->D1 : tlb->D0)

                if (n ? tlb->D1 : tlb->D0) {

                    *prot |= PAGE_WRITE;

                }

                if (!(n ? tlb->XI1 : tlb->XI0)) {

                    *prot |= PAGE_EXEC;

                }
@@ -130,7 +133,7 @@ static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) 
    int32_t adetlb_mask;



    switch (mmu_idx) {

    case 3 /* ERL */:

    case 3: /* ERL */

        /* If EU is set, always unmapped */

        if (eu) {

            return 0;
@@ -252,14 +255,15 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, 
        } else {

            segctl = env->CP0_SegCtl2 >> 16;

        }

        ret = get_segctl_physical_address(env, physical, prot, real_address, rw,

                                          access_type, mmu_idx, segctl,

                                          0x3FFFFFFF);

        ret = get_segctl_physical_address(env, physical, prot,

                                          real_address, rw, access_type,

                                          mmu_idx, segctl, 0x3FFFFFFF);

#if defined(TARGET_MIPS64)

    } else if (address < 0x4000000000000000ULL) {

        /* xuseg */

        if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {

            ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);

            ret = env->tlb->map_address(env, physical, prot,

                                        real_address, rw, access_type);

        } else {

            ret = TLBRET_BADADDR;

        }
@@ -267,7 +271,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, 
        /* xsseg */

        if ((supervisor_mode || kernel_mode) &&

            SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {

            ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);

            ret = env->tlb->map_address(env, physical, prot,

                                        real_address, rw, access_type);

        } else {

            ret = TLBRET_BADADDR;

        }
@@ -307,7 +312,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, 
        /* xkseg */

        if (kernel_mode && KX &&

            address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {

            ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);

            ret = env->tlb->map_address(env, physical, prot,

                                        real_address, rw, access_type);

        } else {

            ret = TLBRET_BADADDR;

        }
@@ -328,8 +334,10 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, 
                                          access_type, mmu_idx,

                                          env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);

    } else {

        /* kseg3 */

        /* XXX: debug segment is not emulated */

        /*

         * kseg3

         * XXX: debug segment is not emulated

         */

        ret = get_segctl_physical_address(env, physical, prot, real_address, rw,

                                          access_type, mmu_idx,

                                          env->CP0_SegCtl0, 0x1FFFFFFF);
@@ -515,9 +523,9 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, 
#if defined(TARGET_MIPS64)

    env->CP0_EntryHi &= env->SEGMask;

    env->CP0_XContext =

        /* PTEBase */   (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |

        /* R */         (extract64(address, 62, 2) << (env->SEGBITS - 9)) |

        /* BadVPN2 */   (extract64(address, 13, env->SEGBITS - 13) << 4);

        (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase */

        (extract64(address, 62, 2) << (env->SEGBITS - 9)) |     /* R       */

        (extract64(address, 13, env->SEGBITS - 13) << 4);       /* BadVPN2 */

#endif

    cs->exception_index = exception;

    env->error_code = error_code;
@@ -945,7 +953,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 
}



#ifndef CONFIG_USER_ONLY

hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)

hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,

                                  int rw)

{

    hwaddr physical;

    int prot;
@@ -1013,8 +1022,10 @@ target_ulong exception_resume_pc (CPUMIPSState *env) 
    isa_mode = !!(env->hflags & MIPS_HFLAG_M16);

    bad_pc = env->active_tc.PC | isa_mode;

    if (env->hflags & MIPS_HFLAG_BMASK) {

        /* If the exception was raised from a delay slot, come back to

           the jump.  */

        /*

         * If the exception was raised from a delay slot, come back to

         * the jump.

         */

        bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);

    }
@@ -1028,8 +1039,8 @@ static void set_hflags_for_handler (CPUMIPSState *env) 
    env->hflags &= ~(MIPS_HFLAG_M16);

    /* ...except that microMIPS lets you choose.  */

    if (env->insn_flags & ASE_MICROMIPS) {

        env->hflags |= (!!(env->CP0_Config3

                           & (1 << CP0C3_ISA_ON_EXC))

        env->hflags |= (!!(env->CP0_Config3 &

                           (1 << CP0C3_ISA_ON_EXC))

                        << MIPS_HFLAG_M16_SHIFT);

    }

}
@@ -1096,10 +1107,12 @@ void mips_cpu_do_interrupt(CPUState *cs) 
    switch (cs->exception_index) {

    case EXCP_DSS:

        env->CP0_Debug |= 1 << CP0DB_DSS;

        /* Debug single step cannot be raised inside a delay slot and

           resume will always occur on the next instruction

           (but we assume the pc has always been updated during

           code translation). */

        /*

         * Debug single step cannot be raised inside a delay slot and

         * resume will always occur on the next instruction

         * (but we assume the pc has always been updated during

         * code translation).

         */

        env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);

        goto enter_debug_mode;

    case EXCP_DINT:
@@ -1111,7 +1124,8 @@ void mips_cpu_do_interrupt(CPUState *cs) 
    case EXCP_DBp:

        env->CP0_Debug |= 1 << CP0DB_DBp;

        /* Setup DExcCode - SDBBP instruction */

        env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 << CP0DB_DEC;

        env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) |

                         (9 << CP0DB_DEC);

        goto set_DEPC;

    case EXCP_DDBS:

        env->CP0_Debug |= 1 << CP0DB_DDBS;
@@ -1132,8 +1146,9 @@ void mips_cpu_do_interrupt(CPUState *cs) 
        env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;

        env->hflags &= ~(MIPS_HFLAG_KSU);

        /* EJTAG probe trap enable is not implemented... */

        if (!(env->CP0_Status & (1 << CP0St_EXL)))

        if (!(env->CP0_Status & (1 << CP0St_EXL))) {

            env->CP0_Cause &= ~(1U << CP0Ca_BD);

        }

        env->active_tc.PC = env->exception_base + 0x480;

        set_hflags_for_handler(env);

        break;
@@ -1159,8 +1174,9 @@ void mips_cpu_do_interrupt(CPUState *cs) 
        }

        env->hflags |= MIPS_HFLAG_CP0;

        env->hflags &= ~(MIPS_HFLAG_KSU);

        if (!(env->CP0_Status & (1 << CP0St_EXL)))

        if (!(env->CP0_Status & (1 << CP0St_EXL))) {

            env->CP0_Cause &= ~(1U << CP0Ca_BD);

        }

        env->active_tc.PC = env->exception_base;

        set_hflags_for_handler(env);

        break;
@@ -1176,12 +1192,16 @@ void mips_cpu_do_interrupt(CPUState *cs) 
                uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;



                if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {

                    /* For VEIC mode, the external interrupt controller feeds

                     * the vector through the CP0Cause IP lines.  */

                    /*

                     * For VEIC mode, the external interrupt controller feeds

                     * the vector through the CP0Cause IP lines.

                     */

                    vector = pending;

                } else {

                    /* Vectored Interrupts

                     * Mask with Status.IM7-IM0 to get enabled interrupts. */

                    /*

                     * Vectored Interrupts

                     * Mask with Status.IM7-IM0 to get enabled interrupts.

                     */

                    pending &= (env->CP0_Status >> CP0St_IM) & 0xff;

                    /* Find the highest-priority interrupt. */

                    while (pending >>= 1) {
@@ -1354,7 +1374,8 @@ void mips_cpu_do_interrupt(CPUState *cs) 


        env->active_tc.PC += offset;

        set_hflags_for_handler(env);

        env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);

        env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) |

                         (cause << CP0Ca_EC);

        break;

    default:

        abort();
@@ -1400,16 +1421,20 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) 
    target_ulong mask;



    tlb = &env->tlb->mmu.r4k.tlb[idx];

    /* The qemu TLB is flushed when the ASID changes, so no need to

       flush these entries again.  */

    /*

     * The qemu TLB is flushed when the ASID changes, so no need to

     * flush these entries again.

     */

    if (tlb->G == 0 && tlb->ASID != ASID) {

        return;

    }



    if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {

        /* For tlbwr, we can shadow the discarded entry into

           a new (fake) TLB entry, as long as the guest can not

           tell that it's there.  */

        /*

         * For tlbwr, we can shadow the discarded entry into

         * a new (fake) TLB entry, as long as the guest can not

         * tell that it's there.

         */

        env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;

        env->tlb->tlb_in_use++;

        return;

target/mips/helper.h

+127 −28
Original line number Diff line number Diff line
@@ -822,6 +822,39 @@ DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32) 
DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32)
@@ -877,6 +910,31 @@ DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32) 
DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32)

DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32)

DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32)

DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32)

DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32)

DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32)
@@ -887,11 +945,80 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) 
DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_asub_s_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_asub_u_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_asub_u_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_asub_u_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_asub_u_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32)



DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32)

DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_sll_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_sra_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_sra_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_sra_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_sra_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_srar_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_srar_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_srar_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_srar_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_srl_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_srl_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_srl_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_srl_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_srlr_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_srlr_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_srlr_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_srlr_d, void, env, i32, i32, i32)



DEF_HELPER_3(msa_move_v, void, env, i32, i32)



DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32)
@@ -929,29 +1056,13 @@ DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32) 
DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)



DEF_HELPER_5(msa_sll_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_sra_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_srl_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_addv_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_max_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_max_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_max_a_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_min_a_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_adds_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_asub_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_asub_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_maddv_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32)
@@ -963,19 +1074,7 @@ DEF_HELPER_5(msa_dpsub_s_df, void, env, i32, i32, i32, i32) 
DEF_HELPER_5(msa_dpsub_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_ilvl_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_ilvev_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_ilvod_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_hadd_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_hadd_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_hsub_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32)



DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)

target/mips/msa_helper.c

+3065 −1586

File changed.

Preview size limit exceeded, changes collapsed.