Commit ee4402ea authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-pullreq-20180905' into staging 



A misc collection of RISC-V related patches for 3.1.

# gpg: Signature made Wed 05 Sep 2018 23:06:55 BST
# gpg:                using RSA key 21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>"
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# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-pullreq-20180905:
  riscv: remove define cpu_init()
  hw/riscv/spike: Set the soc device tree node as a simple-bus
  hw/riscv/virtio: Set the soc device tree node as a simple-bus
  target/riscv: call gen_goto_tb on DISAS_TOO_MANY
  target/riscv: optimize indirect branches
  target/riscv: optimize cross-page direct jumps in softmmu
  RISC-V: Simplify riscv_cpu_local_irqs_pending
  RISC-V: Use atomic_cmpxchg to update PLIC bitmaps
  RISC-V: Improve page table walker spec compliance
  RISC-V: Update address bits to support sv39 and sv48

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents d5a51573 1ca79ece

hw/riscv/sifive_plic.c

+22 −27
Original line number Diff line number Diff line
@@ -81,36 +81,32 @@ static void sifive_plic_print_state(SiFivePLICState *plic) 
    }

}



static

void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool pending)

static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)

{

    qemu_mutex_lock(&plic->lock);

    uint32_t word = irq >> 5;

    if (pending) {

        plic->pending[word] |= (1 << (irq & 31));

    } else {

        plic->pending[word] &= ~(1 << (irq & 31));

    }

    qemu_mutex_unlock(&plic->lock);

    uint32_t old, new, cmp = atomic_read(a);



    do {

        old = cmp;

        new = (old & ~mask) | (value & mask);

        cmp = atomic_cmpxchg(a, old, new);

    } while (old != cmp);



    return old;

}



static

void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool claimed)

static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level)

{

    qemu_mutex_lock(&plic->lock);

    uint32_t word = irq >> 5;

    if (claimed) {

        plic->claimed[word] |= (1 << (irq & 31));

    } else {

        plic->claimed[word] &= ~(1 << (irq & 31));

    atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level);

}

    qemu_mutex_unlock(&plic->lock);



static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)

{

    atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);

}



static

int sifive_plic_num_irqs_pending(SiFivePLICState *plic, uint32_t addrid)

static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid)

{

    int i, j, count = 0;

    int i, j;

    for (i = 0; i < plic->bitfield_words; i++) {

        uint32_t pending_enabled_not_claimed =

            (plic->pending[i] & ~plic->claimed[i]) &
@@ -123,11 +119,11 @@ int sifive_plic_num_irqs_pending(SiFivePLICState *plic, uint32_t addrid) 
            uint32_t prio = plic->source_priority[irq];

            int enabled = pending_enabled_not_claimed & (1 << j);

            if (enabled && prio > plic->target_priority[addrid]) {

                count++;

                return 1;

            }

        }

    }

    return count;

    return 0;

}



static void sifive_plic_update(SiFivePLICState *plic)
@@ -143,7 +139,7 @@ static void sifive_plic_update(SiFivePLICState *plic) 
        if (!env) {

            continue;

        }

        int level = sifive_plic_num_irqs_pending(plic, addrid) > 0;

        int level = sifive_plic_irqs_pending(plic, addrid);

        switch (mode) {

        case PLICMode_M:

            riscv_set_local_interrupt(RISCV_CPU(cpu), MIP_MEIP, level);
@@ -439,7 +435,6 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp) 
    memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,

                          TYPE_SIFIVE_PLIC, plic->aperture_size);

    parse_hart_config(plic);

    qemu_mutex_init(&plic->lock);

    plic->bitfield_words = (plic->num_sources + 31) >> 5;

    plic->source_priority = g_new0(uint32_t, plic->num_sources);

    plic->target_priority = g_new(uint32_t, plic->num_addrs);

hw/riscv/spike.c

+1 −1
Original line number Diff line number Diff line
@@ -90,7 +90,7 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, 


    qemu_fdt_add_subnode(fdt, "/soc");

    qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);

    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-soc");

    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");

    qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);

    qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);

hw/riscv/virt.c

+1 −1
Original line number Diff line number Diff line
@@ -121,7 +121,7 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, 


    qemu_fdt_add_subnode(fdt, "/soc");

    qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);

    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "riscv-virtio-soc");

    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");

    qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);

    qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);

include/hw/riscv/sifive_plic.h

+0 −1
Original line number Diff line number Diff line
@@ -55,7 +55,6 @@ typedef struct SiFivePLICState { 
    uint32_t *pending;

    uint32_t *claimed;

    uint32_t *enable;

    QemuMutex lock;



    /* config */

    char *hart_config;

target/riscv/cpu.h

+4 −5
Original line number Diff line number Diff line
@@ -24,12 +24,12 @@ 
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */

#if defined(TARGET_RISCV64)

#define TARGET_LONG_BITS 64

#define TARGET_PHYS_ADDR_SPACE_BITS 50

#define TARGET_VIRT_ADDR_SPACE_BITS 39

#define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */

#define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */

#elif defined(TARGET_RISCV32)

#define TARGET_LONG_BITS 32

#define TARGET_PHYS_ADDR_SPACE_BITS 34

#define TARGET_VIRT_ADDR_SPACE_BITS 32

#define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */

#define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */

#endif



#define TCG_GUEST_DEFAULT_MO 0
@@ -251,7 +251,6 @@ int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, 
char *riscv_isa_string(RISCVCPU *cpu);

void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);



#define cpu_init(cpu_model) cpu_generic_init(TYPE_RISCV_CPU, cpu_model)

#define cpu_signal_handler cpu_riscv_signal_handler

#define cpu_list riscv_cpu_list

#define cpu_mmu_index riscv_cpu_mmu_index