Commit ee135aa0 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180821' into staging 



ppc patch queue 2018-08-21

Here's my first ppc & spapr pull request for qemu-3.1.  This contains
a bunch of things that have accumulated while 3.0 was in freeze.
Highlights are:
    * SLOF firmware update
    * A number of floating point cleanups from Richard Henderson and
      Yasmin Beatriz
    * A new model for assigning irq numbers on spapr, this is an
      important preliminary step towards implementing the POWER9
      "XIVE" interrupt controller

# gpg: Signature made Tue 21 Aug 2018 05:32:44 BST
# gpg:                using RSA key 6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-3.1-20180821: (26 commits)
  ppc: add DBCR based debugging
  spapr_pci: factorize the use of SPAPR_MACHINE_GET_CLASS()
  mac_newworld: don't use legacy fw_cfg_init_mem() function
  mac_oldworld: don't use legacy fw_cfg_init_mem() function
  40p: don't use legacy fw_cfg_init_mem() function
  qemu-doc: mark ppc/prep machine as deprecated
  hw/ppc: deprecate the machine type 'prep', replaced by '40p'
  spapr: introduce a IRQ controller backend to the machine
  hw/ppc/ppc405_uc: Convert away from old_mmio
  hw/ppc/ppc_boards: Don't use old_mmio for ref405ep_fpga
  hw/ppc/prep: Remove ifdeffed-out stub of XCSR code
  spapr: introduce a fixed IRQ number space
  spapr: Add a pseries-3.1 machine type
  target/ppc: simplify bcdadd/sub functions
  xics: don't include "target/ppc/cpu-qom.h" in "hw/ppc/xics.h"
  vfio/spapr: Allow backing bigger guest IOMMU pages with smaller physical pages
  target/ppc: bcdsub fix sign when result is zero
  target/ppc: Use non-arithmetic conversions for fp load/store
  target/ppc: Honor fpscr_ze semantics and tidy fre, fresqrt
  target/ppc: Tidy helper_fsqrt
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 659b11e7 0e3bf489

hw/ppc/Makefile.objs

+1 −1
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ obj-y += ppc.o ppc_booke.o fdt.o 
obj-$(CONFIG_PSERIES) += spapr.o spapr_caps.o spapr_vio.o spapr_events.o

obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o spapr_rtas.o

obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o

obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o

obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o spapr_irq.o

# IBM PowerNV

obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o pnv_bmc.o

ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)

hw/ppc/mac_newworld.c

+11 −1
Original line number Diff line number Diff line
@@ -454,7 +454,17 @@ static void ppc_core99_init(MachineState *machine) 
    pmac_format_nvram_partition(nvr, 0x2000);

    /* No PCI init: the BIOS will do it */



    fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);

    dev = qdev_create(NULL, TYPE_FW_CFG_MEM);

    fw_cfg = FW_CFG(dev);

    qdev_prop_set_uint32(dev, "data_width", 1);

    qdev_prop_set_bit(dev, "dma_enabled", false);

    object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,

                              OBJECT(fw_cfg), NULL);

    qdev_init_nofail(dev);

    s = SYS_BUS_DEVICE(dev);

    sysbus_mmio_map(s, 0, CFG_ADDR);

    sysbus_mmio_map(s, 1, CFG_ADDR + 2);



    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);

    fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);

    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);

hw/ppc/mac_oldworld.c

+11 −1
Original line number Diff line number Diff line
@@ -309,7 +309,17 @@ static void ppc_heathrow_init(MachineState *machine) 


    /* No PCI init: the BIOS will do it */



    fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);

    dev = qdev_create(NULL, TYPE_FW_CFG_MEM);

    fw_cfg = FW_CFG(dev);

    qdev_prop_set_uint32(dev, "data_width", 1);

    qdev_prop_set_bit(dev, "dma_enabled", false);

    object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,

                              OBJECT(fw_cfg), NULL);

    qdev_init_nofail(dev);

    s = SYS_BUS_DEVICE(dev);

    sysbus_mmio_map(s, 0, CFG_ADDR);

    sysbus_mmio_map(s, 1, CFG_ADDR + 2);



    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);

    fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);

    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);

hw/ppc/ppc405_boards.c

+10 −50
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ struct ref405ep_fpga_t { 
    uint8_t reg1;

};



static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr)

static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)

{

    ref405ep_fpga_t *fpga;

    uint32_t ret;
@@ -87,8 +87,8 @@ static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr) 
    return ret;

}



static void ref405ep_fpga_writeb (void *opaque,

                                  hwaddr addr, uint32_t value)

static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,

                                 unsigned size)

{

    ref405ep_fpga_t *fpga;
@@ -105,54 +105,14 @@ static void ref405ep_fpga_writeb (void *opaque, 
    }

}



static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr)

{

    uint32_t ret;



    ret = ref405ep_fpga_readb(opaque, addr) << 8;

    ret |= ref405ep_fpga_readb(opaque, addr + 1);



    return ret;

}



static void ref405ep_fpga_writew (void *opaque,

                                  hwaddr addr, uint32_t value)

{

    ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);

    ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);

}



static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr)

{

    uint32_t ret;



    ret = ref405ep_fpga_readb(opaque, addr) << 24;

    ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;

    ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;

    ret |= ref405ep_fpga_readb(opaque, addr + 3);



    return ret;

}



static void ref405ep_fpga_writel (void *opaque,

                                  hwaddr addr, uint32_t value)

{

    ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);

    ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);

    ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);

    ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);

}



static const MemoryRegionOps ref405ep_fpga_ops = {

    .old_mmio = {

        .read = {

            ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl,

        },

        .write = {

            ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel,

        },

    },

    .endianness = DEVICE_NATIVE_ENDIAN,

    .read = ref405ep_fpga_readb,

    .write = ref405ep_fpga_writeb,

    .impl.min_access_size = 1,

    .impl.max_access_size = 1,

    .valid.min_access_size = 1,

    .valid.max_access_size = 4,

    .endianness = DEVICE_BIG_ENDIAN,

};



static void ref405ep_fpga_reset (void *opaque)

hw/ppc/ppc405_uc.c

+25 −148
Original line number Diff line number Diff line
@@ -283,7 +283,7 @@ struct ppc4xx_opba_t { 
    uint8_t pr;

};



static uint32_t opba_readb (void *opaque, hwaddr addr)

static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)

{

    ppc4xx_opba_t *opba;

    uint32_t ret;
@@ -307,8 +307,8 @@ static uint32_t opba_readb (void *opaque, hwaddr addr) 
    return ret;

}



static void opba_writeb (void *opaque,

                         hwaddr addr, uint32_t value)

static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,

                        unsigned size)

{

    ppc4xx_opba_t *opba;
@@ -328,61 +328,14 @@ static void opba_writeb (void *opaque, 
        break;

    }

}



static uint32_t opba_readw (void *opaque, hwaddr addr)

{

    uint32_t ret;



#ifdef DEBUG_OPBA

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

#endif

    ret = opba_readb(opaque, addr) << 8;

    ret |= opba_readb(opaque, addr + 1);



    return ret;

}



static void opba_writew (void *opaque,

                         hwaddr addr, uint32_t value)

{

#ifdef DEBUG_OPBA

    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,

           value);

#endif

    opba_writeb(opaque, addr, value >> 8);

    opba_writeb(opaque, addr + 1, value);

}



static uint32_t opba_readl (void *opaque, hwaddr addr)

{

    uint32_t ret;



#ifdef DEBUG_OPBA

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

#endif

    ret = opba_readb(opaque, addr) << 24;

    ret |= opba_readb(opaque, addr + 1) << 16;



    return ret;

}



static void opba_writel (void *opaque,

                         hwaddr addr, uint32_t value)

{

#ifdef DEBUG_OPBA

    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,

           value);

#endif

    opba_writeb(opaque, addr, value >> 24);

    opba_writeb(opaque, addr + 1, value >> 16);

}



static const MemoryRegionOps opba_ops = {

    .old_mmio = {

        .read = { opba_readb, opba_readw, opba_readl, },

        .write = { opba_writeb, opba_writew, opba_writel, },

    },

    .endianness = DEVICE_NATIVE_ENDIAN,

    .read = opba_readb,

    .write = opba_writeb,

    .impl.min_access_size = 1,

    .impl.max_access_size = 1,

    .valid.min_access_size = 1,

    .valid.max_access_size = 4,

    .endianness = DEVICE_BIG_ENDIAN,

};



static void ppc4xx_opba_reset (void *opaque)
@@ -750,65 +703,27 @@ struct ppc405_gpio_t { 
    uint32_t isr1l;

};



static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)

static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)

{

#ifdef DEBUG_GPIO

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

    printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size);

#endif



    return 0;

}



static void ppc405_gpio_writeb (void *opaque,

                                hwaddr addr, uint32_t value)

{

#ifdef DEBUG_GPIO

    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,

           value);

#endif

}



static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)

static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value,

                              unsigned size)

{

#ifdef DEBUG_GPIO

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

#endif



    return 0;

}



static void ppc405_gpio_writew (void *opaque,

                                hwaddr addr, uint32_t value)

{

#ifdef DEBUG_GPIO

    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,

           value);

#endif

}



static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)

{

#ifdef DEBUG_GPIO

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

#endif



    return 0;

}



static void ppc405_gpio_writel (void *opaque,

                                hwaddr addr, uint32_t value)

{

#ifdef DEBUG_GPIO

    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,

           value);

    printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n",

           __func__, addr, size, value);

#endif

}



static const MemoryRegionOps ppc405_gpio_ops = {

    .old_mmio = {

        .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },

        .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },

    },

    .read = ppc405_gpio_read,

    .write = ppc405_gpio_write,

    .endianness = DEVICE_NATIVE_ENDIAN,

};
@@ -1017,44 +932,6 @@ struct ppc4xx_gpt_t { 
    uint32_t mask[5];

};



static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)

{

#ifdef DEBUG_GPT

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

#endif

    /* XXX: generate a bus fault */

    return -1;

}



static void ppc4xx_gpt_writeb (void *opaque,

                               hwaddr addr, uint32_t value)

{

#ifdef DEBUG_I2C

    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,

           value);

#endif

    /* XXX: generate a bus fault */

}



static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)

{

#ifdef DEBUG_GPT

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

#endif

    /* XXX: generate a bus fault */

    return -1;

}



static void ppc4xx_gpt_writew (void *opaque,

                               hwaddr addr, uint32_t value)

{

#ifdef DEBUG_I2C

    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,

           value);

#endif

    /* XXX: generate a bus fault */

}



static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)

{

    /* XXX: TODO */
@@ -1107,7 +984,7 @@ static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) 
    /* XXX: TODO */

}



static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)

static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)

{

    ppc4xx_gpt_t *gpt;

    uint32_t ret;
@@ -1162,8 +1039,8 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr) 
    return ret;

}



static void ppc4xx_gpt_writel (void *opaque,

                               hwaddr addr, uint32_t value)

static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,

                             unsigned size)

{

    ppc4xx_gpt_t *gpt;

    int idx;
@@ -1225,10 +1102,10 @@ static void ppc4xx_gpt_writel (void *opaque, 
}



static const MemoryRegionOps gpt_ops = {

    .old_mmio = {

        .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },

        .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },

    },

    .read = ppc4xx_gpt_read,

    .write = ppc4xx_gpt_write,

    .valid.min_access_size = 4,

    .valid.max_access_size = 4,

    .endianness = DEVICE_NATIVE_ENDIAN,

};