Unverified Commit ed5abf46 authored Jan 20, 2020 by Alistair Francis Committed by Palmer Dabbelt Mar 16, 2020

target/riscv: Correctly implement TSR trap

As reported in: https://bugs.launchpad.net/qemu/+bug/1851939

 we weren't
correctly handling illegal instructions based on the value of MSTATUS_TSR
and the current privledge level.

This patch fixes the issue raised in the bug by raising an illegal
instruction if TSR is set and we are in S-Mode.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Jonathan Behrens <jonathan@fintelia.io>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

parent a98135f7

target/riscv/op_helper.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -85,7 +85,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
		}

		if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
		get_field(env->mstatus, MSTATUS_TSR)) {
		get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
		riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
		}