Commit ece628fc authored by Peter Maydell's avatar Peter Maydell
Browse files

hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots 

If we're booting a Linux kernel directly into Non-Secure
state on a CPU which has Secure state, then make sure we
set the NSACR CP11 and CP10 bits, so that Non-Secure is allowed
to access the FPU. Otherwise an AArch32 kernel will UNDEF as
soon as it tries to use the FPU.

It used to not matter that we didn't do this until commit
fc1120a7, where we implemented actually honouring
these NSACR bits.

The problem only exists for CPUs where EL3 is AArch32; the
equivalent AArch64 trap bits are in CPTR_EL3 and are "0 to
not trap, 1 to trap", so the reset value of the register
permits NS access, unlike NSACR.

Fixes: fc1120a7
Fixes: https://bugs.launchpad.net/qemu/+bug/1844597


Cc: qemu-stable@nongnu.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190920174039.3916-1-peter.maydell@linaro.org
parent 83704cef

hw/arm/boot.c

+2 −0
Original line number Diff line number Diff line
@@ -754,6 +754,8 @@ static void do_cpu_reset(void *opaque) 
                    (cs != first_cpu || !info->secure_board_setup)) {

                    /* Linux expects non-secure state */

                    env->cp15.scr_el3 |= SCR_NS;

                    /* Set NSACR.{CP11,CP10} so NS can access the FPU */

                    env->cp15.nsacr |= 3 << 10;

                }

            }