Commit ec97eb61 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191022-2' into staging 



 * Fix sign-extension for SMLAL* instructions
 * Various ptimer device conversions to new transaction API
 * Add a dummy Samsung SDHCI controller model to exynos4 boards
 * Minor refactorings of RAM creation for some arm boards

# gpg: Signature made Tue 22 Oct 2019 17:44:26 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20191022-2:
  hw/arm/digic4: Inline digic4_board_setup_ram() function
  hw/arm/omap1: Create the RAM in the board
  hw/arm/omap2: Create the RAM in the board
  hw/arm/collie: Create the RAM in the board
  hw/arm/mps2: Use the IEC binary prefix definitions
  hw/arm/xilinx_zynq: Use the IEC binary prefix definitions
  hw/arm/exynos4210: Use the Samsung s3c SDHCI controller
  hw/sd/sdhci: Add dummy Samsung SDHCI controller
  hw/sd/sdhci: Add a comment to distinct the i.MX eSDHC functions
  hw/m68k/mcf5208.c: Switch to transaction-based ptimer API
  hw/watchdog/etraxfs_timer.c: Switch to transaction-based ptimer API
  hw/timer/altera_timer.c: Switch to transaction-based ptimer API
  hw/timer/lm32_timer: Switch to transaction-based ptimer API
  hw/timer/sh_timer: Switch to transaction-based ptimer API
  hw/timer/puv3_ost.c: Switch to transaction-based ptimer API
  hw/timer/arm_mptimer.c: Undo accidental rename of arm_mptimer_init()
  hw/timer/exynos4210_mct: Initialize ptimer before starting it
  target/arm: Fix sign-extension for SMLAL*

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents f9bec781 90600829

hw/arm/collie.c

+6 −2
Original line number Diff line number Diff line
@@ -27,9 +27,13 @@ static void collie_init(MachineState *machine) 
{

    StrongARMState *s;

    DriveInfo *dinfo;

    MemoryRegion *sysmem = get_system_memory();

    MemoryRegion *sdram = g_new(MemoryRegion, 1);



    s = sa1110_init(sysmem, collie_binfo.ram_size, machine->cpu_type);

    s = sa1110_init(machine->cpu_type);



    memory_region_allocate_system_memory(sdram, NULL, "strongarm.sdram",

                                         collie_binfo.ram_size);

    memory_region_add_subregion(get_system_memory(), SA_SDCS0, sdram);



    dinfo = drive_get(IF_PFLASH, 0, 0);

    pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000,

hw/arm/digic_boards.c

+2 −7
Original line number Diff line number Diff line
@@ -53,12 +53,6 @@ typedef struct DigicBoard { 
    const char *rom1_def_filename;

} DigicBoard;



static void digic4_board_setup_ram(DigicBoardState *s, hwaddr ram_size)

{

    memory_region_allocate_system_memory(&s->ram, NULL, "ram", ram_size);

    memory_region_add_subregion(get_system_memory(), 0, &s->ram);

}



static void digic4_board_init(DigicBoard *board)

{

    Error *err = NULL;
@@ -72,7 +66,8 @@ static void digic4_board_init(DigicBoard *board) 
        exit(1);

    }



    digic4_board_setup_ram(s, board->ram_size);

    memory_region_allocate_system_memory(&s->ram, NULL, "ram", board->ram_size);

    memory_region_add_subregion(get_system_memory(), 0, &s->ram);



    if (board->add_rom0) {

        board->add_rom0(s, DIGIC4_ROM0_BASE, board->rom0_def_filename);

hw/arm/exynos4210.c

+1 −1
Original line number Diff line number Diff line
@@ -405,7 +405,7 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) 
         * public datasheet which is very similar (implementing

         * MMC Specification Version 4.0 being the only difference noted)

         */

        dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);

        dev = qdev_create(NULL, TYPE_S3C_SDHCI);

        qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES);

        qdev_init_nofail(dev);

hw/arm/mps2-tz.c

+2 −1
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 
 */



#include "qemu/osdep.h"

#include "qemu/units.h"

#include "qapi/error.h"

#include "qemu/error-report.h"

#include "hw/arm/boot.h"
@@ -458,7 +459,7 @@ static void mps2tz_common_init(MachineState *machine) 
     * call the 16MB our "system memory", as it's the largest lump.

     */

    memory_region_allocate_system_memory(&mms->psram,

                                         NULL, "mps.ram", 0x01000000);

                                         NULL, "mps.ram", 16 * MiB);

    memory_region_add_subregion(system_memory, 0x80000000, &mms->psram);



    /* The overflow IRQs for all UARTs are ORed together.

hw/arm/mps2.c

+2 −1
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
 */



#include "qemu/osdep.h"

#include "qemu/units.h"

#include "qapi/error.h"

#include "qemu/error-report.h"

#include "hw/arm/boot.h"
@@ -146,7 +147,7 @@ static void mps2_common_init(MachineState *machine) 
     * zbt_boot_ctrl is always zero).

     */

    memory_region_allocate_system_memory(&mms->psram,

                                         NULL, "mps.ram", 0x1000000);

                                         NULL, "mps.ram", 16 * MiB);

    memory_region_add_subregion(system_memory, 0x21000000, &mms->psram);



    switch (mmc->fpga_type) {