Commit ebae861f authored by Philippe Mathieu-Daudé's avatar Philippe Mathieu-Daudé Committed by Peter Maydell
Browse files

target/arm: Declare get_phys_addr() function publicly 



In the next commit we will split the TLB related routines of
this file, and this function will also be called in the new
file. Declare it in the "internals.h" header.

Signed-off-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190701132516.26392-12-philmd@redhat.com
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 86480615

target/arm/helper.c

+5 −16
Original line number Diff line number Diff line
@@ -33,17 +33,6 @@ 
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */



#ifndef CONFIG_USER_ONLY

/* Cacheability and shareability attributes for a memory access */

typedef struct ARMCacheAttrs {

    unsigned int attrs:8; /* as in the MAIR register encoding */

    unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */

} ARMCacheAttrs;



static bool get_phys_addr(CPUARMState *env, target_ulong address,

                          MMUAccessType access_type, ARMMMUIdx mmu_idx,

                          hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,

                          target_ulong *page_size,

                          ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);



static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,

                               MMUAccessType access_type, ARMMMUIdx mmu_idx,
@@ -12639,7 +12628,7 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) 
 * @fi: set to fault info if the translation fails

 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes

 */

static bool get_phys_addr(CPUARMState *env, target_ulong address,

bool get_phys_addr(CPUARMState *env, target_ulong address,

                   MMUAccessType access_type, ARMMMUIdx mmu_idx,

                   hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,

                   target_ulong *page_size,

target/arm/internals.h

+16 −0
Original line number Diff line number Diff line
@@ -985,4 +985,20 @@ static inline int exception_target_el(CPUARMState *env) 
    return target_el;

}



#ifndef CONFIG_USER_ONLY



/* Cacheability and shareability attributes for a memory access */

typedef struct ARMCacheAttrs {

    unsigned int attrs:8; /* as in the MAIR register encoding */

    unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */

} ARMCacheAttrs;



bool get_phys_addr(CPUARMState *env, target_ulong address,

                   MMUAccessType access_type, ARMMMUIdx mmu_idx,

                   hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,

                   target_ulong *page_size,

                   ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);



#endif /* !CONFIG_USER_ONLY */



#endif