Commit eb821168 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement data cache set allocation tags 



This is DC GVA and DC GZVA, and the tag check for DC ZVA.

Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-40-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent c4af8ba1

target/arm/cpu.h

+3 −1
Original line number Diff line number Diff line
@@ -2360,7 +2360,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 
#define ARM_CP_NZCV              (ARM_CP_SPECIAL | 0x0300)

#define ARM_CP_CURRENTEL         (ARM_CP_SPECIAL | 0x0400)

#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)

#define ARM_LAST_SPECIAL         ARM_CP_DC_ZVA

#define ARM_CP_DC_GVA            (ARM_CP_SPECIAL | 0x0600)

#define ARM_CP_DC_GZVA           (ARM_CP_SPECIAL | 0x0700)

#define ARM_LAST_SPECIAL         ARM_CP_DC_GZVA

#define ARM_CP_FPU               0x1000

#define ARM_CP_SVE               0x2000

#define ARM_CP_NO_GDB            0x4000

target/arm/helper.c

+16 −0
Original line number Diff line number Diff line
@@ -6998,6 +6998,22 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { 
      .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,

      .type = ARM_CP_NOP, .access = PL0_W,

      .accessfn = aa64_cacheop_poc_access },

    { .name = "DC_GVA", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3,

      .access = PL0_W, .type = ARM_CP_DC_GVA,

#ifndef CONFIG_USER_ONLY

      /* Avoid overhead of an access check that always passes in user-mode */

      .accessfn = aa64_zva_access,

#endif

    },

    { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4,

      .access = PL0_W, .type = ARM_CP_DC_GZVA,

#ifndef CONFIG_USER_ONLY

      /* Avoid overhead of an access check that always passes in user-mode */

      .accessfn = aa64_zva_access,

#endif

    },

    REGINFO_SENTINEL

};

target/arm/translate-a64.c

+39 −0
Original line number Diff line number Diff line
@@ -1874,6 +1874,45 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, 
        }

        gen_helper_dc_zva(cpu_env, tcg_rt);

        return;

    case ARM_CP_DC_GVA:

        {

            TCGv_i64 clean_addr, tag;



            /*

             * DC_GVA, like DC_ZVA, requires that we supply the original

             * pointer for an invalid page.  Probe that address first.

             */

            tcg_rt = cpu_reg(s, rt);

            clean_addr = clean_data_tbi(s, tcg_rt);

            gen_probe_access(s, clean_addr, MMU_DATA_STORE, MO_8);



            if (s->ata) {

                /* Extract the tag from the register to match STZGM.  */

                tag = tcg_temp_new_i64();

                tcg_gen_shri_i64(tag, tcg_rt, 56);

                gen_helper_stzgm_tags(cpu_env, clean_addr, tag);

                tcg_temp_free_i64(tag);

            }

        }

        return;

    case ARM_CP_DC_GZVA:

        {

            TCGv_i64 clean_addr, tag;



            /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */

            tcg_rt = cpu_reg(s, rt);

            clean_addr = clean_data_tbi(s, tcg_rt);

            gen_helper_dc_zva(cpu_env, clean_addr);



            if (s->ata) {

                /* Extract the tag from the register to match STZGM.  */

                tag = tcg_temp_new_i64();

                tcg_gen_shri_i64(tag, tcg_rt, 56);

                gen_helper_stzgm_tags(cpu_env, clean_addr, tag);

                tcg_temp_free_i64(tag);

            }

        }

        return;

    default:

        break;

    }