Commit eb6ea4b2 authored by Nathan Whitehorn's avatar Nathan Whitehorn Committed by Alexander Graf
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PPC: Fix large page support in TCG 



Fix large page support in TCG. The old code would overwrite the large page
table entry with the fake 4 KB one generated here whenever the ref/change bits
were updated, causing it to point to the wrong area of memory.

Signed-off-by: default avatarNathan Whitehorn <nwhitehorn@freebsd.org>
Acked-by: default avatarDavid Gibson <david@gibson.drobpear.id.au>
[agraf: fix whitespace, braces]
Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
parent 2e06214f

target-ppc/helper.c

+6 −6
Original line number Diff line number Diff line
@@ -591,12 +591,6 @@ static inline int _find_pte(CPUPPCState *env, mmu_ctx_t *ctx, int is_64b, int h, 
                pte1 = ldq_phys(env->htab_base + pteg_off + (i * 16) + 8);

            }



            /* We have a TLB that saves 4K pages, so let's

             * split a huge page to 4k chunks */

            if (target_page_bits != TARGET_PAGE_BITS)

                pte1 |= (ctx->eaddr & (( 1 << target_page_bits ) - 1))

                        & TARGET_PAGE_MASK;



            r = pte64_check(ctx, pte0, pte1, h, rw, type);

            LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "

                    TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
@@ -672,6 +666,12 @@ static inline int _find_pte(CPUPPCState *env, mmu_ctx_t *ctx, int is_64b, int h, 
        }

    }



    /* We have a TLB that saves 4K pages, so let's

     * split a huge page to 4k chunks */

    if (target_page_bits != TARGET_PAGE_BITS) {

        ctx->raddr |= (ctx->eaddr & ((1 << target_page_bits) - 1))

                      & TARGET_PAGE_MASK;

    }

    return ret;

}