Commit eabb5782 authored by Peter Xu's avatar Peter Xu Committed by Paolo Bonzini
Browse files

hw/misc/edu: support MSI interrupt 



So now edu device can support both line or msi interrupt, depending on
how user configures it.

Signed-off-by: default avatarPeter Xu <peterx@redhat.com>
Message-Id: <1475067819-21413-1-git-send-email-peterx@redhat.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 3cf294ee

docs/specs/edu.txt

+6 −1
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ size == 8 for the rest. 


0x20 (RW) : status register, bitwise OR

	    0x01 -- computing factorial (RO)

	    0x80 -- raise interrupt 0x01 after finishing factorial computation

	    0x80 -- raise interrupt after finishing factorial computation



0x24 (RO) : interrupt status register

	    It contains values which raised the interrupt (see interrupt raise
@@ -87,6 +87,11 @@ An IRQ is generated when written to the interrupt raise register. The value 
appears in interrupt status register when the interrupt is raised and has to

be written to the interrupt acknowledge register to lower it.



The device supports both INTx and MSI interrupt. By default, INTx is

used. Even if the driver disabled INTx and only uses MSI, it still

needs to update the acknowledge register at the end of the IRQ handler

routine.



DMA controller

--------------

One has to specify, source, destination, size, and start the transfer. One

hw/misc/edu.c

+16 −2
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 


#include "qemu/osdep.h"

#include "hw/pci/pci.h"

#include "hw/pci/msi.h"

#include "qemu/timer.h"

#include "qemu/main-loop.h" /* iothread mutex */

#include "qapi/visitor.h"
@@ -69,19 +70,28 @@ typedef struct { 
    uint64_t dma_mask;

} EduState;



static bool edu_msi_enabled(EduState *edu)

{

    return msi_enabled(&edu->pdev);

}



static void edu_raise_irq(EduState *edu, uint32_t val)

{

    edu->irq_status |= val;

    if (edu->irq_status) {

        if (edu_msi_enabled(edu)) {

            msi_notify(&edu->pdev, 0);

        } else {

            pci_set_irq(&edu->pdev, 1);

        }

    }

}



static void edu_lower_irq(EduState *edu, uint32_t val)

{

    edu->irq_status &= ~val;



    if (!edu->irq_status) {

    if (!edu->irq_status && !edu_msi_enabled(edu)) {

        pci_set_irq(&edu->pdev, 0);

    }

}
@@ -342,6 +352,10 @@ static void pci_edu_realize(PCIDevice *pdev, Error **errp) 


    pci_config_set_interrupt_pin(pci_conf, 1);



    if (msi_init(pdev, 0, 1, true, false, errp)) {

        return;

    }



    memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,

                    "edu-mmio", 1 << 20);

    pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio);