Commit ea96b374 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Simplify op_smlaxxx for SMLAL* 



Since all of the inputs and outputs are i32, dispense with
the intermediate promotion to i64 and use tcg_gen_add2_i32.

Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-11-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 26c6923d

target/arm/translate.c

+8 −7
Original line number Diff line number Diff line
@@ -8177,8 +8177,7 @@ DO_QADDSUB(QDSUB, false, true) 
static bool op_smlaxxx(DisasContext *s, arg_rrrr *a,

                       int add_long, bool nt, bool mt)

{

    TCGv_i32 t0, t1;

    TCGv_i64 t64;

    TCGv_i32 t0, t1, tl, th;



    if (s->thumb

        ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
@@ -8202,12 +8201,14 @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, 
        store_reg(s, a->rd, t0);

        break;

    case 2:

        t64 = tcg_temp_new_i64();

        tcg_gen_ext_i32_i64(t64, t0);

        tl = load_reg(s, a->ra);

        th = load_reg(s, a->rd);

        t1 = tcg_const_i32(0);

        tcg_gen_add2_i32(tl, th, tl, th, t0, t1);

        tcg_temp_free_i32(t0);

        gen_addq(s, t64, a->ra, a->rd);

        gen_storeq_reg(s, a->ra, a->rd, t64);

        tcg_temp_free_i64(t64);

        tcg_temp_free_i32(t1);

        store_reg(s, a->ra, tl);

        store_reg(s, a->rd, th);

        break;

    default:

        g_assert_not_reached();