Commit e9d65282 authored by Philippe Mathieu-Daudé's avatar Philippe Mathieu-Daudé Committed by Peter Maydell
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target/arm/vfp_helper: Extract vfp_set_fpscr_to_host() 



The vfp_set_fpscr() helper contains code specific to the host
floating point implementation (here the SoftFloat library).
Extract this code to vfp_set_fpscr_to_host().

Signed-off-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190701132516.26392-16-philmd@redhat.com
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 20e62dd8

target/arm/vfp_helper.c

+53 −48
Original line number Diff line number Diff line
@@ -81,6 +81,58 @@ static inline int vfp_exceptbits_to_host(int target_bits) 
    return host_bits;

}



static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)

{

    int i;

    uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];



    changed ^= val;

    if (changed & (3 << 22)) {

        i = (val >> 22) & 3;

        switch (i) {

        case FPROUNDING_TIEEVEN:

            i = float_round_nearest_even;

            break;

        case FPROUNDING_POSINF:

            i = float_round_up;

            break;

        case FPROUNDING_NEGINF:

            i = float_round_down;

            break;

        case FPROUNDING_ZERO:

            i = float_round_to_zero;

            break;

        }

        set_float_rounding_mode(i, &env->vfp.fp_status);

        set_float_rounding_mode(i, &env->vfp.fp_status_f16);

    }

    if (changed & FPCR_FZ16) {

        bool ftz_enabled = val & FPCR_FZ16;

        set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);

        set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);

    }

    if (changed & FPCR_FZ) {

        bool ftz_enabled = val & FPCR_FZ;

        set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);

        set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);

    }

    if (changed & FPCR_DN) {

        bool dnan_enabled = val & FPCR_DN;

        set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);

        set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);

    }



    /*

     * The exception flags are ORed together when we read fpscr so we

     * only need to preserve the current state in one of our

     * float_status values.

     */

    i = vfp_exceptbits_to_host(val);

    set_float_exception_flags(i, &env->vfp.fp_status);

    set_float_exception_flags(0, &env->vfp.fp_status_f16);

    set_float_exception_flags(0, &env->vfp.standard_fp_status);

}



uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)

{

    uint32_t i, fpscr;
@@ -109,9 +161,6 @@ uint32_t vfp_get_fpscr(CPUARMState *env) 


void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)

{

    int i;

    uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];



    /* When ARMv8.2-FP16 is not supported, FZ16 is RES0.  */

    if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) {

        val &= ~FPCR_FZ16;
@@ -146,51 +195,7 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) 
    env->vfp.qc[2] = 0;

    env->vfp.qc[3] = 0;



    changed ^= val;

    if (changed & (3 << 22)) {

        i = (val >> 22) & 3;

        switch (i) {

        case FPROUNDING_TIEEVEN:

            i = float_round_nearest_even;

            break;

        case FPROUNDING_POSINF:

            i = float_round_up;

            break;

        case FPROUNDING_NEGINF:

            i = float_round_down;

            break;

        case FPROUNDING_ZERO:

            i = float_round_to_zero;

            break;

        }

        set_float_rounding_mode(i, &env->vfp.fp_status);

        set_float_rounding_mode(i, &env->vfp.fp_status_f16);

    }

    if (changed & FPCR_FZ16) {

        bool ftz_enabled = val & FPCR_FZ16;

        set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);

        set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);

    }

    if (changed & FPCR_FZ) {

        bool ftz_enabled = val & FPCR_FZ;

        set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);

        set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);

    }

    if (changed & FPCR_DN) {

        bool dnan_enabled = val & FPCR_DN;

        set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);

        set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);

    }



    /*

     * The exception flags are ORed together when we read fpscr so we

     * only need to preserve the current state in one of our

     * float_status values.

     */

    i = vfp_exceptbits_to_host(val);

    set_float_exception_flags(i, &env->vfp.fp_status);

    set_float_exception_flags(0, &env->vfp.fp_status_f16);

    set_float_exception_flags(0, &env->vfp.standard_fp_status);

    vfp_set_fpscr_to_host(env, val);

}



void vfp_set_fpscr(CPUARMState *env, uint32_t val)