Commit e9d1a53a authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg/ppc: Add support for vector saturated add/subtract 



Add support for vector saturated add/subtract using Altivec
instructions:
VADDSBS, VADDSHS, VADDSWS, VADDUBS, VADDUHS, VADDUWS, and
VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBS, VSUBUHS, VSUBUWS.

Tested-by: default avatarMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
parent d6750811

tcg/ppc/tcg-target.h

+1 −1
Original line number Diff line number Diff line
@@ -163,7 +163,7 @@ extern bool have_altivec; 
#define TCG_TARGET_HAS_shv_vec          0

#define TCG_TARGET_HAS_cmp_vec          1

#define TCG_TARGET_HAS_mul_vec          0

#define TCG_TARGET_HAS_sat_vec          0

#define TCG_TARGET_HAS_sat_vec          1

#define TCG_TARGET_HAS_minmax_vec       1

#define TCG_TARGET_HAS_bitsel_vec       0

#define TCG_TARGET_HAS_cmpsel_vec       0

tcg/ppc/tcg-target.inc.c

+36 −0
Original line number Diff line number Diff line
@@ -471,12 +471,24 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, 
#define STVX       XO31(231)

#define STVEWX     XO31(199)



#define VADDSBS    VX4(768)

#define VADDUBS    VX4(512)

#define VADDUBM    VX4(0)

#define VADDSHS    VX4(832)

#define VADDUHS    VX4(576)

#define VADDUHM    VX4(64)

#define VADDSWS    VX4(896)

#define VADDUWS    VX4(640)

#define VADDUWM    VX4(128)



#define VSUBSBS    VX4(1792)

#define VSUBUBS    VX4(1536)

#define VSUBUBM    VX4(1024)

#define VSUBSHS    VX4(1856)

#define VSUBUHS    VX4(1600)

#define VSUBUHM    VX4(1088)

#define VSUBSWS    VX4(1920)

#define VSUBUWS    VX4(1664)

#define VSUBUWM    VX4(1152)



#define VMAXSB     VX4(258)
@@ -2844,6 +2856,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 
    case INDEX_op_smin_vec:

    case INDEX_op_umax_vec:

    case INDEX_op_umin_vec:

    case INDEX_op_ssadd_vec:

    case INDEX_op_sssub_vec:

    case INDEX_op_usadd_vec:

    case INDEX_op_ussub_vec:

        return vece <= MO_32;

    case INDEX_op_cmp_vec:

        return vece <= MO_32 ? -1 : 0;
@@ -2945,6 +2961,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 
        eq_op[4]  = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },

        gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },

        gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },

        ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },

        usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 },

        sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 },

        ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 },

        umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },

        smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },

        umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },
@@ -2971,6 +2991,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 
    case INDEX_op_sub_vec:

        insn = sub_op[vece];

        break;

    case INDEX_op_ssadd_vec:

        insn = ssadd_op[vece];

        break;

    case INDEX_op_sssub_vec:

        insn = sssub_op[vece];

        break;

    case INDEX_op_usadd_vec:

        insn = usadd_op[vece];

        break;

    case INDEX_op_ussub_vec:

        insn = ussub_op[vece];

        break;

    case INDEX_op_smin_vec:

        insn = smin_op[vece];

        break;
@@ -3277,6 +3309,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) 
    case INDEX_op_andc_vec:

    case INDEX_op_orc_vec:

    case INDEX_op_cmp_vec:

    case INDEX_op_ssadd_vec:

    case INDEX_op_sssub_vec:

    case INDEX_op_usadd_vec:

    case INDEX_op_ussub_vec:

    case INDEX_op_smax_vec:

    case INDEX_op_smin_vec:

    case INDEX_op_umax_vec: