Commit e905587b authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging 



virtio, vhost, pci: fixes, features

generic pci root port support
disable shpc by default
safer version of ARRAY_SIZE and QEMU_BUILD_BUG_ON
fixes and cleanups all over the place

Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Wed 01 Feb 2017 01:38:34 GMT
# gpg:                using RSA key 0x281F0DB8D28D5469
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>"
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>"
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* remotes/mst/tags/for_upstream: (22 commits)
  arm: add trailing ; after MISMATCH_CHECK
  arm: better stub version for MISMATCH_CHECK
  hw/pci: disable pci-bridge's shpc by default
  vhost-user: delete chardev on cleanup
  vhost: skip ROM sections
  virtio: make virtio_should_notify static
  pci: Convert msix_init() to Error and fix callers
  hcd-xhci: check & correct param before using it
  msix: Follow CODING_STYLE
  hw/i386: check if nvdimm is enabled before plugging
  hw/pcie: Introduce Generic PCI Express Root Port
  hw/ioh3420: derive from PCI Express Root Port base class
  hw/pcie: Introduce a base class for PCI Express Root Ports
  intel_iommu: fix and simplify size calculation in process_device_iotlb_desc()
  pci: mark ROMs read-only
  ARRAY_SIZE: check that argument is an array
  compiler: expression version of QEMU_BUILD_BUG_ON
  compiler: rework BUG_ON using a struct
  QEMU_BUILD_BUG_ON: use __COUNTER__
  ppc: switch to constants within BUILD_BUG_ON
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 2d6752d3 1b28762a

default-configs/arm-softmmu.mak

+1 −0
Original line number Diff line number Diff line
@@ -108,6 +108,7 @@ CONFIG_FSL_IMX25=y 


CONFIG_IMX_I2C=y



CONFIG_PCIE_PORT=y

CONFIG_XIO3130=y

CONFIG_IOH3420=y

CONFIG_I82801B11=y

default-configs/i386-softmmu.mak

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ CONFIG_PVPANIC=y 
CONFIG_MEM_HOTPLUG=y

CONFIG_NVDIMM=y

CONFIG_ACPI_NVDIMM=y

CONFIG_PCIE_PORT=y

CONFIG_XIO3130=y

CONFIG_IOH3420=y

CONFIG_I82801B11=y

default-configs/x86_64-softmmu.mak

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ CONFIG_PVPANIC=y 
CONFIG_MEM_HOTPLUG=y

CONFIG_NVDIMM=y

CONFIG_ACPI_NVDIMM=y

CONFIG_PCIE_PORT=y

CONFIG_XIO3130=y

CONFIG_IOH3420=y

CONFIG_I82801B11=y

hw/block/nvme.c

+1 −1
Original line number Diff line number Diff line
@@ -872,7 +872,7 @@ static int nvme_init(PCIDevice *pci_dev) 
    pci_register_bar(&n->parent_obj, 0,

        PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64,

        &n->iomem);

    msix_init_exclusive_bar(&n->parent_obj, n->num_queues, 4);

    msix_init_exclusive_bar(&n->parent_obj, n->num_queues, 4, NULL);



    id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));

    id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));

hw/display/qxl.c

+4 −5
Original line number Diff line number Diff line
@@ -306,12 +306,11 @@ void qxl_spice_reset_cursor(PCIQXLDevice *qxl) 


static ram_addr_t qxl_rom_size(void)

{

    uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) +

                                 sizeof(qxl_modes);

    uint32_t rom_size = 8192; /* two pages */

#define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes))

#define QXL_ROM_SZ 8192



    QEMU_BUILD_BUG_ON(required_rom_size > rom_size);

    return rom_size;

    QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ);

    return QXL_ROM_SZ;

}



static void init_qxl_rom(PCIQXLDevice *d)