Commit e85c0d14 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging 



pc: fixes, cleanups, features

Some fixes and cleanups. Extended TSEG sizes.

Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Fri 16 Jun 2017 16:45:07 BST
# gpg:                using RSA key 0x281F0DB8D28D5469
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>"
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>"
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* remotes/mst/tags/for_upstream:
  hw/i386: fix nvdimm check error path
  intel_iommu: cleanup vtd_interrupt_remap_msi()
  intel_iommu: cleanup vtd_{do_}iommu_translate()
  intel_iommu: switching the rest DPRINTF to trace
  tests/q35-test: add TSEG size checks
  tests/q35-test: push down qtest_start / qtest_end to test case(s)
  q35/mch: implement extended TSEG sizes

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 65a0e3e8 7f3cf2d6

hw/i386/intel_iommu.c

+151 −270

File changed.

Preview size limit exceeded, changes collapsed.

hw/i386/intel_iommu_internal.h

+1 −0
Original line number Diff line number Diff line
@@ -384,6 +384,7 @@ typedef struct VTDIOTLBPageInvInfo VTDIOTLBPageInvInfo; 
/* Pagesize of VTD paging structures, including root and context tables */

#define VTD_PAGE_SHIFT              12

#define VTD_PAGE_SIZE               (1ULL << VTD_PAGE_SHIFT)

#define VTD_PAGE_MASK               (VTD_PAGE_SIZE - 1)



#define VTD_PAGE_SHIFT_4K           12

#define VTD_PAGE_MASK_4K            (~((1ULL << VTD_PAGE_SHIFT_4K) - 1))

hw/i386/pc.c

+8 −6
Original line number Diff line number Diff line
@@ -1692,6 +1692,7 @@ static void pc_dimm_plug(HotplugHandler *hotplug_dev, 
    PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);

    MemoryRegion *mr = ddc->get_memory_region(dimm);

    uint64_t align = TARGET_PAGE_SIZE;

    bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);



    if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) {

        align = memory_region_get_alignment(mr);
@@ -1703,17 +1704,18 @@ static void pc_dimm_plug(HotplugHandler *hotplug_dev, 
        goto out;

    }



    pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err);

    if (local_err) {

    if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) {

        error_setg(&local_err,

                   "nvdimm is not enabled: missing 'nvdimm' in '-M'");

        goto out;

    }



    if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {

        if (!pcms->acpi_nvdimm_state.is_enabled) {

            error_setg(&local_err,

                       "nvdimm is not enabled: missing 'nvdimm' in '-M'");

    pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err);

    if (local_err) {

        goto out;

    }



    if (is_nvdimm) {

        nvdimm_plug(&pcms->acpi_nvdimm_state);

    }

hw/i386/trace-events

+44 −0
Original line number Diff line number Diff line
@@ -19,6 +19,13 @@ vtd_inv_desc_wait_sw(uint64_t addr, uint32_t data) "wait invalidate status write 
vtd_inv_desc_wait_irq(const char *msg) "%s"

vtd_inv_desc_wait_invalid(uint64_t hi, uint64_t lo) "invalid wait desc hi 0x%"PRIx64" lo 0x%"PRIx64

vtd_inv_desc_wait_write_fail(uint64_t hi, uint64_t lo) "write fail for wait desc hi 0x%"PRIx64" lo 0x%"PRIx64

vtd_inv_desc_iec(uint32_t granularity, uint32_t index, uint32_t mask) "granularity 0x%"PRIx32" index 0x%"PRIx32" mask 0x%"PRIx32

vtd_inv_qi_enable(bool enable) "enabled %d"

vtd_inv_qi_setup(uint64_t addr, int size) "addr 0x%"PRIx64" size %d"

vtd_inv_qi_head(uint16_t head) "read head %d"

vtd_inv_qi_tail(uint16_t head) "write tail %d"

vtd_inv_qi_fetch(void) ""

vtd_context_cache_reset(void) ""

vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present"

vtd_re_invalid(uint64_t hi, uint64_t lo) "invalid root entry hi 0x%"PRIx64" lo 0x%"PRIx64

vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8" devfn %"PRIu8" not present"
@@ -40,6 +47,43 @@ vtd_switch_address_space(uint8_t bus, uint8_t slot, uint8_t fn, bool on) "Device 
vtd_as_unmap_whole(uint8_t bus, uint8_t slot, uint8_t fn, uint64_t iova, uint64_t size) "Device %02x:%02x.%x start 0x%"PRIx64" size 0x%"PRIx64

vtd_translate_pt(uint16_t sid, uint64_t addr) "source id 0x%"PRIu16", iova 0x%"PRIx64

vtd_pt_enable_fast_path(uint16_t sid, bool success) "sid 0x%"PRIu16" %d"

vtd_irq_generate(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" data 0x%"PRIx64

vtd_reg_read(uint64_t addr, uint64_t size) "addr 0x%"PRIx64" size 0x%"PRIx64

vtd_reg_write(uint64_t addr, uint64_t size, uint64_t val) "addr 0x%"PRIx64" size 0x%"PRIx64" value 0x%"PRIx64

vtd_reg_dmar_root(uint64_t addr, bool extended) "addr 0x%"PRIx64" extended %d"

vtd_reg_ir_root(uint64_t addr, uint32_t size) "addr 0x%"PRIx64" size 0x%"PRIx32

vtd_reg_write_gcmd(uint32_t status, uint32_t val) "status 0x%"PRIx32" value 0x%"PRIx32

vtd_reg_write_fectl(uint32_t value) "value 0x%"PRIx32

vtd_reg_write_iectl(uint32_t value) "value 0x%"PRIx32

vtd_reg_ics_clear_ip(void) ""

vtd_dmar_translate(uint8_t bus, uint8_t slot, uint8_t func, uint64_t iova, uint64_t gpa, uint64_t mask) "dev %02x:%02x.%02x iova 0x%"PRIx64" -> gpa 0x%"PRIx64" mask 0x%"PRIx64

vtd_dmar_enable(bool en) "enable %d"

vtd_dmar_fault(uint16_t sid, int fault, uint64_t addr, bool is_write) "sid 0x%"PRIx16" fault %d addr 0x%"PRIx64" write %d"

vtd_ir_enable(bool en) "enable %d"

vtd_ir_irte_get(int index, uint64_t lo, uint64_t hi) "index %d low 0x%"PRIx64" high 0x%"PRIx64

vtd_ir_remap(int index, int tri, int vec, int deliver, uint32_t dest, int dest_mode) "index %d trigger %d vector %d deliver %d dest 0x%"PRIx32" mode %d"

vtd_ir_remap_type(const char *type) "%s"

vtd_ir_remap_msi(uint64_t addr, uint64_t data, uint64_t addr2, uint64_t data2) "(addr 0x%"PRIx64", data 0x%"PRIx64") -> (addr 0x%"PRIx64", data 0x%"PRIx64")"

vtd_ir_remap_msi_req(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" data 0x%"PRIx64

vtd_fsts_ppf(bool set) "FSTS PPF bit set to %d"

vtd_fsts_clear_ip(void) ""

vtd_frr_new(int index, uint64_t hi, uint64_t lo) "index %d high 0x%"PRIx64" low 0x%"PRIx64

vtd_err(const char *str) "%s"

vtd_err_dmar_iova_overflow(uint64_t iova) "iova 0x%"PRIx64

vtd_err_dmar_slpte_read_error(uint64_t iova, int level) "iova 0x%"PRIx64" level %d"

vtd_err_dmar_slpte_perm_error(uint64_t iova, int level, uint64_t slpte, bool is_write) "iova 0x%"PRIx64" level %d slpte 0x%"PRIx64" write %d"

vtd_err_dmar_slpte_resv_error(uint64_t iova, int level, uint64_t slpte) "iova 0x%"PRIx64" level %d slpte 0x%"PRIx64

vtd_err_dmar_translate(uint8_t bus, uint8_t slot, uint8_t func, uint64_t iova) "dev %02x:%02x.%02x iova 0x%"PRIx64

vtd_err_qi_enable(uint16_t tail) "tail 0x%"PRIx16

vtd_err_qi_disable(uint16_t head, uint16_t tail, int type) "head 0x%"PRIx16" tail 0x%"PRIx16" last_desc_type %d"

vtd_err_qi_tail(uint16_t tail, uint16_t size) "tail 0x%"PRIx16" size 0x%"PRIx16

vtd_err_irte(int index, uint64_t lo, uint64_t hi) "index %d low 0x%"PRIx64" high 0x%"PRIx64

vtd_err_irte_sid(int index, uint16_t req, uint16_t target) "index %d SVT_ALL sid 0x%"PRIx16" (should be: 0x%"PRIx16")"

vtd_err_irte_sid_bus(int index, uint8_t bus, uint8_t min, uint8_t max) "index %d SVT_BUS bus 0x%"PRIx8" (should be: 0x%"PRIx8"-0x%"PRIx8")"

vtd_err_irte_svt(int index, int type) "index %d SVT type %d"

vtd_err_ir_msi_invalid(uint16_t sid, uint64_t addr, uint64_t data) "sid 0x%"PRIx16" addr 0x%"PRIx64" data 0x%"PRIx64

vtd_warn_ir_vector(uint16_t sid, int index, int vec, int target) "sid 0x%"PRIx16" index %d vec %d (should be: %d)"

vtd_warn_ir_trigger(uint16_t sid, int index, int trig, int target) "sid 0x%"PRIx16" index %d trigger %d (should be: %d)"



# hw/i386/amd_iommu.c

amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at addr 0x%"PRIx64" +  offset 0x%"PRIx32

hw/pci-host/q35.c

+38 −3
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 
    visit_type_uint32(v, name, &value, errp);

}



static Property mch_props[] = {

static Property q35_host_props[] = {

    DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,

                        MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),

    DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
@@ -154,7 +154,7 @@ static void q35_host_class_init(ObjectClass *klass, void *data) 


    hc->root_bus_path = q35_host_root_bus_path;

    dc->realize = q35_host_realize;

    dc->props = mch_props;

    dc->props = q35_host_props;

    /* Reason: needs to be wired up by pc_q35_init */

    dc->user_creatable = false;

    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
@@ -369,7 +369,7 @@ static void mch_update_smram(MCHPCIState *mch) 
            tseg_size = 1024 * 1024 * 8;

            break;

        default:

            tseg_size = 0;

            tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes;

            break;

        }

    } else {
@@ -392,6 +392,17 @@ static void mch_update_smram(MCHPCIState *mch) 
    memory_region_transaction_commit();

}



static void mch_update_ext_tseg_mbytes(MCHPCIState *mch)

{

    PCIDevice *pd = PCI_DEVICE(mch);

    uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES;



    if (mch->ext_tseg_mbytes > 0 &&

        pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) {

        pci_set_word(reg, mch->ext_tseg_mbytes);

    }

}



static void mch_write_config(PCIDevice *d,

                              uint32_t address, uint32_t val, int len)

{
@@ -413,6 +424,11 @@ static void mch_write_config(PCIDevice *d, 
                       MCH_HOST_BRIDGE_SMRAM_SIZE)) {

        mch_update_smram(mch);

    }



    if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES,

                       MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) {

        mch_update_ext_tseg_mbytes(mch);

    }

}



static void mch_update(MCHPCIState *mch)
@@ -420,6 +436,7 @@ static void mch_update(MCHPCIState *mch) 
    mch_update_pciexbar(mch);

    mch_update_pam(mch);

    mch_update_smram(mch);

    mch_update_ext_tseg_mbytes(mch);

}



static int mch_post_load(void *opaque, int version_id)
@@ -457,6 +474,11 @@ static void mch_reset(DeviceState *qdev) 
    d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK;

    d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK;



    if (mch->ext_tseg_mbytes > 0) {

        pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES,

                     MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY);

    }



    mch_update(mch);

}
@@ -465,6 +487,12 @@ static void mch_realize(PCIDevice *d, Error **errp) 
    int i;

    MCHPCIState *mch = MCH_PCI_DEVICE(d);



    if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) {

        error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16,

                   mch->ext_tseg_mbytes);

        return;

    }



    /* setup pci memory mapping */

    pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory,

                           mch->pci_address_space);
@@ -530,6 +558,12 @@ uint64_t mch_mcfg_base(void) 
    return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;

}



static Property mch_props[] = {

    DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes,

                       16),

    DEFINE_PROP_END_OF_LIST(),

};



static void mch_class_init(ObjectClass *klass, void *data)

{

    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
@@ -538,6 +572,7 @@ static void mch_class_init(ObjectClass *klass, void *data) 
    k->realize = mch_realize;

    k->config_write = mch_write_config;

    dc->reset = mch_reset;

    dc->props = mch_props;

    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);

    dc->desc = "Host bridge";

    dc->vmsd = &vmstate_mch;