Commit e72e3ffc authored by Peter Maydell's avatar Peter Maydell
Browse files

hw/armv7m_nvic: Use LOG_GUEST_ERROR and LOG_UNIMP 



Use LOG_GUEST_ERROR and LOG_UNIMP rather than hw_error() where
appropriate.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent edb94a41

hw/armv7m_nvic.c

+19 −12
Original line number Diff line number Diff line
@@ -234,7 +234,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) 
        return val;

    case 0xd28: /* Configurable Fault Status.  */

        /* TODO: Implement Fault Status.  */

        hw_error("Not implemented: Configurable Fault Status.");

        qemu_log_mask(LOG_UNIMP, "Configurable Fault Status unimplemented\n");

        return 0;

    case 0xd2c: /* Hard Fault Status.  */

    case 0xd30: /* Debug Fault Status.  */
@@ -242,7 +242,8 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) 
    case 0xd38: /* Bus Fault Address.  */

    case 0xd3c: /* Aux Fault Status.  */

        /* TODO: Implement fault status registers.  */

        goto bad_reg;

        qemu_log_mask(LOG_UNIMP, "Fault status registers unimplemented\n");

        return 0;

    case 0xd40: /* PFR0.  */

        return 0x00000030;

    case 0xd44: /* PRF1.  */
@@ -271,8 +272,8 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) 
        return 0x01310102;

    /* TODO: Implement debug registers.  */

    default:

    bad_reg:

        hw_error("NVIC: Bad read offset 0x%x\n", offset);

        qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);

        return 0;

    }

}
@@ -335,17 +336,18 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) 
    case 0xd0c: /* Application Interrupt/Reset Control.  */

        if ((value >> 16) == 0x05fa) {

            if (value & 2) {

                hw_error("VECTCLRACTIVE not implemented");

                qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n");

            }

            if (value & 5) {

                hw_error("System reset");

                qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");

            }

        }

        break;

    case 0xd10: /* System Control.  */

    case 0xd14: /* Configuration Control.  */

        /* TODO: Implement control registers.  */

        goto bad_reg;

        qemu_log_mask(LOG_UNIMP, "NVIC: SCR and CCR unimplemented\n");

        break;

    case 0xd24: /* System Handler Control.  */

        /* TODO: Real hardware allows you to set/clear the active bits

           under some circumstances.  We don't implement this.  */
@@ -359,15 +361,17 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) 
    case 0xd34: /* Mem Manage Address.  */

    case 0xd38: /* Bus Fault Address.  */

    case 0xd3c: /* Aux Fault Status.  */

        goto bad_reg;

        qemu_log_mask(LOG_UNIMP,

                      "NVIC: fault status registers unimplemented\n");

        break;

    case 0xf00: /* Software Triggered Interrupt Register */

        if ((value & 0x1ff) < s->num_irq) {

            gic_set_pending_private(&s->gic, 0, value & 0x1ff);

        }

        break;

    default:

    bad_reg:

        hw_error("NVIC: Bad write offset 0x%x\n", offset);

        qemu_log_mask(LOG_GUEST_ERROR,

                      "NVIC: Bad write offset 0x%x\n", offset);

    }

}
@@ -395,7 +399,9 @@ static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr, 
    if (size == 4) {

        return nvic_readl(s, offset);

    }

    hw_error("NVIC: Bad read of size %d at offset 0x%x\n", size, offset);

    qemu_log_mask(LOG_GUEST_ERROR,

                  "NVIC: Bad read of size %d at offset 0x%x\n", size, offset);

    return 0;

}



static void nvic_sysreg_write(void *opaque, hwaddr addr,
@@ -418,7 +424,8 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, 
        nvic_writel(s, offset, value);

        return;

    }

    hw_error("NVIC: Bad write of size %d at offset 0x%x\n", size, offset);

    qemu_log_mask(LOG_GUEST_ERROR,

                  "NVIC: Bad write of size %d at offset 0x%x\n", size, offset);

}



static const MemoryRegionOps nvic_sysreg_ops = {