Loading hw/acpi/ich9.c +1 −1 Original line number Diff line number Diff line Loading @@ -166,7 +166,7 @@ const VMStateDescription vmstate_ich9_pm = { VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs), VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs), VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs), VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs), VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, ICH9LPCPMRegs), VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs), VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs), VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs), Loading hw/acpi/piix4.c +1 −1 Original line number Diff line number Diff line Loading @@ -285,7 +285,7 @@ static const VMStateDescription vmstate_acpi = { VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), VMSTATE_STRUCT_TEST( Loading hw/arm/stellaris.c +1 −1 Original line number Diff line number Diff line Loading @@ -306,7 +306,7 @@ static const VMStateDescription vmstate_stellaris_gptm = { VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), VMSTATE_UINT32(rtc, gptm_state), VMSTATE_INT64_ARRAY(tick, gptm_state, 2), VMSTATE_TIMER_ARRAY(timer, gptm_state, 2), VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), VMSTATE_END_OF_LIST() } }; Loading hw/block/fdc.c +1 −1 Original line number Diff line number Diff line Loading @@ -791,7 +791,7 @@ static const VMStateDescription vmstate_fdc_result_timer = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_TIMER(result_timer, FDCtrl), VMSTATE_TIMER_PTR(result_timer, FDCtrl), VMSTATE_END_OF_LIST() } }; Loading hw/char/cadence_uart.c +1 −1 Original line number Diff line number Diff line Loading @@ -520,7 +520,7 @@ static const VMStateDescription vmstate_cadence_uart = { VMSTATE_UINT32(rx_count, UartState), VMSTATE_UINT32(tx_count, UartState), VMSTATE_UINT32(rx_wpos, UartState), VMSTATE_TIMER(fifo_trigger_handle, UartState), VMSTATE_TIMER_PTR(fifo_trigger_handle, UartState), VMSTATE_END_OF_LIST() } }; Loading Loading
hw/acpi/ich9.c +1 −1 Original line number Diff line number Diff line Loading @@ -166,7 +166,7 @@ const VMStateDescription vmstate_ich9_pm = { VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs), VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs), VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs), VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs), VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, ICH9LPCPMRegs), VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs), VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs), VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs), Loading
hw/acpi/piix4.c +1 −1 Original line number Diff line number Diff line Loading @@ -285,7 +285,7 @@ static const VMStateDescription vmstate_acpi = { VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState), VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), VMSTATE_STRUCT_TEST( Loading
hw/arm/stellaris.c +1 −1 Original line number Diff line number Diff line Loading @@ -306,7 +306,7 @@ static const VMStateDescription vmstate_stellaris_gptm = { VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), VMSTATE_UINT32(rtc, gptm_state), VMSTATE_INT64_ARRAY(tick, gptm_state, 2), VMSTATE_TIMER_ARRAY(timer, gptm_state, 2), VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), VMSTATE_END_OF_LIST() } }; Loading
hw/block/fdc.c +1 −1 Original line number Diff line number Diff line Loading @@ -791,7 +791,7 @@ static const VMStateDescription vmstate_fdc_result_timer = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_TIMER(result_timer, FDCtrl), VMSTATE_TIMER_PTR(result_timer, FDCtrl), VMSTATE_END_OF_LIST() } }; Loading
hw/char/cadence_uart.c +1 −1 Original line number Diff line number Diff line Loading @@ -520,7 +520,7 @@ static const VMStateDescription vmstate_cadence_uart = { VMSTATE_UINT32(rx_count, UartState), VMSTATE_UINT32(tx_count, UartState), VMSTATE_UINT32(rx_wpos, UartState), VMSTATE_TIMER(fifo_trigger_handle, UartState), VMSTATE_TIMER_PTR(fifo_trigger_handle, UartState), VMSTATE_END_OF_LIST() } }; Loading