Commit e69ad9df authored by Aaron Lindsay's avatar Aaron Lindsay Committed by Peter Maydell
Browse files

target/arm: Allow EL change hooks to do IO 



During code generation, surround CPSR writes and exception returns which
call the EL change hooks with gen_io_start/end. The immediate need is
for the PMU to access the clock and icount during EL change to support
mode filtering.

Signed-off-by: default avatarAaron Lindsay <alindsay@codeaurora.org>
Message-id: 1523997485-1905-9-git-send-email-alindsay@codeaurora.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent b5c53d1b

target/arm/translate-a64.c

+6 −0
Original line number Diff line number Diff line
@@ -1930,7 +1930,13 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) 
            unallocated_encoding(s);

            return;

        }

        if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {

            gen_io_start();

        }

        gen_helper_exception_return(cpu_env);

        if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {

            gen_io_end();

        }

        /* Must exit loop to check un-masked IRQs */

        s->base.is_jmp = DISAS_EXIT;

        return;

target/arm/translate.c

+12 −0
Original line number Diff line number Diff line
@@ -4548,7 +4548,13 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr) 
     * appropriately depending on the new Thumb bit, so it must

     * be called after storing the new PC.

     */

    if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {

        gen_io_start();

    }

    gen_helper_cpsr_write_eret(cpu_env, cpsr);

    if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {

        gen_io_end();

    }

    tcg_temp_free_i32(cpsr);

    /* Must exit loop to check un-masked IRQs */

    s->base.is_jmp = DISAS_EXIT;
@@ -9843,7 +9849,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) 
                if (exc_return) {

                    /* Restore CPSR from SPSR.  */

                    tmp = load_cpu_field(spsr);

                    if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {

                        gen_io_start();

                    }

                    gen_helper_cpsr_write_eret(cpu_env, tmp);

                    if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {

                        gen_io_end();

                    }

                    tcg_temp_free_i32(tmp);

                    /* Must exit loop to check un-masked IRQs */

                    s->base.is_jmp = DISAS_EXIT;