Commit e678c56f authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160922' into staging 



target-arm queue:
 * add Cortex-A7 CPU
 * new ast2500 SoC model and evaluation board
 * palmetto-bmc: remove stray double assignment
 * aspeed: clean up RAM size handling
 * ptimer: framework for defining policy bits to change
   behaviour choices for different timer devices
 * ptimer: add some test cases
 * cadence_gem: add queue support
 * loader: support loading images to specified address spaces
 * loader: support auto-detect of ELF architecture from file
 * dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX
 * vmstateify ssd0323
 * vmstateify ssi-sd
 * disas/arm.c: remove unused macros
 * imx: use 'const char', not 'char const'

# gpg: Signature made Thu 22 Sep 2016 18:20:22 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20160922: (36 commits)
  imx: Use 'const char', not 'char const'
  disas/arm.c: Remove unused macro definitions
  vmstateify ssi-sd
  vmstateify ssd0323 display
  dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX
  loader: Add AddressSpace loading support to targphys
  loader: Add AddressSpace loading support to uImages
  loader: Add AddressSpace loading support to ELFs
  loader: Allow a custom AddressSpace when loading ROMs
  loader: Use the specified MemoryRegion
  loader: Allow ELF loader to auto-detect the ELF arch
  xlnx-zynqmp: Set the number of priority queues
  cadence_gem: Correct indentation
  cadence_gem: Add queue support
  cadence_gem: Add support for screening
  cadence_gem: Add the num-priority-queues property
  cadence_gem: QOMify Cadence GEM
  tests: Add ptimer tests
  hw/ptimer: Suppress error messages under qtest
  hw/ptimer: Introduce timer policy feature
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 430da7a8 d675765a

disas/arm.c

+0 −11
Original line number Diff line number Diff line
@@ -24,7 +24,6 @@ 


#include "qemu/osdep.h"

#include "disas/bfd.h"

#define ISSPACE(x) ((x) == ' ' || (x) == '\t' || (x) == '\n')



#define ARM_EXT_V1	 0

#define ARM_EXT_V2	 0
@@ -73,15 +72,6 @@ static void floatformat_to_double (unsigned char *data, double *dest) 


/* End of qemu specific additions.  */



/* FIXME: Belongs in global header.  */

#ifndef strneq

#define strneq(a,b,n)	(strncmp ((a), (b), (n)) == 0)

#endif



#ifndef NUM_ELEM

#define NUM_ELEM(a)     (sizeof (a) / sizeof (a)[0])

#endif



struct opcode32

{

  unsigned long arch;		/* Architecture defining this insn.  */
@@ -1528,7 +1518,6 @@ static const char *const iwmmxt_cregnames[] = 
/* Default to GCC register name set.  */

static unsigned int regname_selected = 1;



#define NUM_ARM_REGNAMES  NUM_ELEM (regnames)

#define arm_regnames      regnames[regname_selected].reg_names



static bfd_boolean force_thumb = false;

hw/arm/Makefile.objs

+1 −1
Original line number Diff line number Diff line
@@ -17,4 +17,4 @@ obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o 
obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o

obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o

obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o

obj-$(CONFIG_ASPEED_SOC) += ast2400.o palmetto-bmc.o
 
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o

hw/arm/palmetto-bmc.c→hw/arm/aspeed.c

+197 −0
Original line number Diff line number Diff line
@@ -15,24 +15,61 @@ 
#include "cpu.h"

#include "exec/address-spaces.h"

#include "hw/arm/arm.h"

#include "hw/arm/ast2400.h"

#include "hw/arm/aspeed_soc.h"

#include "hw/boards.h"

#include "qemu/log.h"

#include "sysemu/block-backend.h"

#include "sysemu/blockdev.h"



static struct arm_boot_info palmetto_bmc_binfo = {

    .loader_start = AST2400_SDRAM_BASE,

    .board_id = 0,

static struct arm_boot_info aspeed_board_binfo = {

    .board_id = -1, /* device-tree-only board */

    .nb_cpus = 1,

};



typedef struct PalmettoBMCState {

    AST2400State soc;

typedef struct AspeedBoardState {

    AspeedSoCState soc;

    MemoryRegion ram;

} PalmettoBMCState;

} AspeedBoardState;



static void palmetto_bmc_init_flashes(AspeedSMCState *s, const char *flashtype,

typedef struct AspeedBoardConfig {

    const char *soc_name;

    uint32_t hw_strap1;

} AspeedBoardConfig;



enum {

    PALMETTO_BMC,

    AST2500_EVB,

};



#define PALMETTO_BMC_HW_STRAP1 (                                        \

        SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |               \

        SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \

        SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \

        SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \

        SCU_HW_STRAP_VGA_CLASS_CODE |                                   \

        SCU_HW_STRAP_LPC_RESET_PIN |                                    \

        SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \

        SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \

        SCU_HW_STRAP_SPI_WIDTH |                                        \

        SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \

        SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))



#define AST2500_EVB_HW_STRAP1 ((                                        \

        AST2500_HW_STRAP1_DEFAULTS |                                    \

        SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \

        SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \

        SCU_AST2500_HW_STRAP_UART_DEBUG |                               \

        SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \

        SCU_HW_STRAP_MAC1_RGMII |                                       \

        SCU_HW_STRAP_MAC0_RGMII) &                                      \

        ~SCU_HW_STRAP_2ND_BOOT_WDT)



static const AspeedBoardConfig aspeed_boards[] = {

    [PALMETTO_BMC] = { "ast2400-a0", PALMETTO_BMC_HW_STRAP1 },

    [AST2500_EVB]  = { "ast2500-a1", AST2500_EVB_HW_STRAP1 },

};



static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,

                                      Error **errp)

{

    int i ;
@@ -58,45 +95,103 @@ static void palmetto_bmc_init_flashes(AspeedSMCState *s, const char *flashtype, 
    }

}



static void palmetto_bmc_init(MachineState *machine)

static void aspeed_board_init(MachineState *machine,

                              const AspeedBoardConfig *cfg)

{

    PalmettoBMCState *bmc;

    AspeedBoardState *bmc;

    AspeedSoCClass *sc;



    bmc = g_new0(PalmettoBMCState, 1);

    object_initialize(&bmc->soc, (sizeof(bmc->soc)), TYPE_AST2400);

    bmc = g_new0(AspeedBoardState, 1);

    object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name);

    object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc),

                              &error_abort);



    memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);

    memory_region_add_subregion(get_system_memory(), AST2400_SDRAM_BASE,

                                &bmc->ram);

    object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),

    sc = ASPEED_SOC_GET_CLASS(&bmc->soc);



    object_property_set_int(OBJECT(&bmc->soc), ram_size, "ram-size",

                           &error_abort);

    object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1",

    object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1",

                            &error_abort);

    object_property_set_bool(OBJECT(&bmc->soc), true, "realized",

                             &error_abort);



    palmetto_bmc_init_flashes(&bmc->soc.smc, "n25q256a", &error_abort);

    palmetto_bmc_init_flashes(&bmc->soc.spi, "mx25l25635e", &error_abort);

    /*

     * Allocate RAM after the memory controller has checked the size

     * was valid. If not, a default value is used.

     */

    ram_size = object_property_get_int(OBJECT(&bmc->soc), "ram-size",

                                       &error_abort);



    palmetto_bmc_binfo.kernel_filename = machine->kernel_filename;

    palmetto_bmc_binfo.initrd_filename = machine->initrd_filename;

    palmetto_bmc_binfo.kernel_cmdline = machine->kernel_cmdline;

    palmetto_bmc_binfo.ram_size = ram_size;

    arm_load_kernel(ARM_CPU(first_cpu), &palmetto_bmc_binfo);

    memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);

    memory_region_add_subregion(get_system_memory(), sc->info->sdram_base,

                                &bmc->ram);

    object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),

                                   &error_abort);



    aspeed_board_init_flashes(&bmc->soc.smc, "n25q256a", &error_abort);

    aspeed_board_init_flashes(&bmc->soc.spi, "mx25l25635e", &error_abort);



    aspeed_board_binfo.kernel_filename = machine->kernel_filename;

    aspeed_board_binfo.initrd_filename = machine->initrd_filename;

    aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;

    aspeed_board_binfo.ram_size = ram_size;

    aspeed_board_binfo.loader_start = sc->info->sdram_base;



    arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo);

}



static void palmetto_bmc_machine_init(MachineClass *mc)

static void palmetto_bmc_init(MachineState *machine)

{

    mc->desc = "OpenPOWER Palmetto BMC";

    aspeed_board_init(machine, &aspeed_boards[PALMETTO_BMC]);

}



static void palmetto_bmc_class_init(ObjectClass *oc, void *data)

{

    MachineClass *mc = MACHINE_CLASS(oc);



    mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";

    mc->init = palmetto_bmc_init;

    mc->max_cpus = 1;

    mc->no_sdcard = 1;

    mc->no_floppy = 1;

    mc->no_cdrom = 1;

    mc->no_parallel = 1;

}



static const TypeInfo palmetto_bmc_type = {

    .name = MACHINE_TYPE_NAME("palmetto-bmc"),

    .parent = TYPE_MACHINE,

    .class_init = palmetto_bmc_class_init,

};



static void ast2500_evb_init(MachineState *machine)

{

    aspeed_board_init(machine, &aspeed_boards[AST2500_EVB]);

}



static void ast2500_evb_class_init(ObjectClass *oc, void *data)

{

    MachineClass *mc = MACHINE_CLASS(oc);



    mc->desc = "Aspeed AST2500 EVB (ARM1176)";

    mc->init = ast2500_evb_init;

    mc->max_cpus = 1;

    mc->no_sdcard = 1;

    mc->no_floppy = 1;

    mc->no_cdrom = 1;

    mc->no_parallel = 1;

}



DEFINE_MACHINE("palmetto-bmc", palmetto_bmc_machine_init);
 
static const TypeInfo ast2500_evb_type = {

    .name = MACHINE_TYPE_NAME("ast2500-evb"),

    .parent = TYPE_MACHINE,

    .class_init = ast2500_evb_class_init,

};



static void aspeed_machine_init(void)

{

    type_register_static(&palmetto_bmc_type);

    type_register_static(&ast2500_evb_type);

}



type_init(aspeed_machine_init)

hw/arm/ast2400.c→hw/arm/aspeed_soc.c

+78 −53
Original line number Diff line number Diff line 
/*

 * AST2400 SoC

 * ASPEED SoC family

 *

 * Andrew Jeffery <andrew@aj.id.au>

 * Jeremy Kerr <jk@ozlabs.org>
@@ -15,59 +15,68 @@ 
#include "qemu-common.h"

#include "cpu.h"

#include "exec/address-spaces.h"

#include "hw/arm/ast2400.h"

#include "hw/arm/aspeed_soc.h"

#include "hw/char/serial.h"

#include "qemu/log.h"

#include "hw/i2c/aspeed_i2c.h"



#define AST2400_UART_5_BASE      0x00184000

#define AST2400_IOMEM_SIZE       0x00200000

#define AST2400_IOMEM_BASE       0x1E600000

#define AST2400_SMC_BASE         AST2400_IOMEM_BASE /* Legacy SMC */

#define AST2400_FMC_BASE         0X1E620000

#define AST2400_SPI_BASE         0X1E630000

#define AST2400_VIC_BASE         0x1E6C0000

#define AST2400_SDMC_BASE        0x1E6E0000

#define AST2400_SCU_BASE         0x1E6E2000

#define AST2400_TIMER_BASE       0x1E782000

#define AST2400_I2C_BASE         0x1E78A000



#define AST2400_FMC_FLASH_BASE   0x20000000

#define AST2400_SPI_FLASH_BASE   0x30000000

#define ASPEED_SOC_UART_5_BASE      0x00184000

#define ASPEED_SOC_IOMEM_SIZE       0x00200000

#define ASPEED_SOC_IOMEM_BASE       0x1E600000

#define ASPEED_SOC_FMC_BASE         0x1E620000

#define ASPEED_SOC_SPI_BASE         0x1E630000

#define ASPEED_SOC_VIC_BASE         0x1E6C0000

#define ASPEED_SOC_SDMC_BASE        0x1E6E0000

#define ASPEED_SOC_SCU_BASE         0x1E6E2000

#define ASPEED_SOC_TIMER_BASE       0x1E782000

#define ASPEED_SOC_I2C_BASE         0x1E78A000



#define ASPEED_SOC_FMC_FLASH_BASE   0x20000000

#define ASPEED_SOC_SPI_FLASH_BASE   0x30000000



static const int uart_irqs[] = { 9, 32, 33, 34, 10 };

static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };



#define AST2400_SDRAM_BASE       0x40000000

#define AST2500_SDRAM_BASE       0x80000000



static const AspeedSoCInfo aspeed_socs[] = {

    { "ast2400-a0", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE },

    { "ast2400",    "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE },

    { "ast2500-a1", "arm1176", AST2500_A1_SILICON_REV, AST2500_SDRAM_BASE },

};



/*

 * IO handlers: simply catch any reads/writes to IO addresses that aren't

 * handled by a device mapping.

 */



static uint64_t ast2400_io_read(void *p, hwaddr offset, unsigned size)

static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size)

{

    qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",

                  __func__, offset, size);

    return 0;

}



static void ast2400_io_write(void *opaque, hwaddr offset, uint64_t value,

static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value,

                unsigned size)

{

    qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",

                  __func__, offset, value, size);

}



static const MemoryRegionOps ast2400_io_ops = {

    .read = ast2400_io_read,

    .write = ast2400_io_write,

static const MemoryRegionOps aspeed_soc_io_ops = {

    .read = aspeed_soc_io_read,

    .write = aspeed_soc_io_write,

    .endianness = DEVICE_LITTLE_ENDIAN,

};



static void ast2400_init(Object *obj)

static void aspeed_soc_init(Object *obj)

{

    AST2400State *s = AST2400(obj);

    AspeedSoCState *s = ASPEED_SOC(obj);

    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);



    s->cpu = cpu_arm_init("arm926");

    s->cpu = cpu_arm_init(sc->info->cpu_model);



    object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);

    object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
@@ -85,7 +94,7 @@ static void ast2400_init(Object *obj) 
    object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);

    qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());

    qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",

                         AST2400_A0_SILICON_REV);

                         sc->info->silicon_rev);

    object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),

                              "hw-strap1", &error_abort);

    object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
@@ -103,20 +112,22 @@ static void ast2400_init(Object *obj) 
    object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);

    qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());

    qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",

                         AST2400_A0_SILICON_REV);

                         sc->info->silicon_rev);

    object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),

                              "ram-size", &error_abort);

}



static void ast2400_realize(DeviceState *dev, Error **errp)

static void aspeed_soc_realize(DeviceState *dev, Error **errp)

{

    int i;

    AST2400State *s = AST2400(dev);

    AspeedSoCState *s = ASPEED_SOC(dev);

    Error *err = NULL, *local_err = NULL;



    /* IO space */

    memory_region_init_io(&s->iomem, NULL, &ast2400_io_ops, NULL,

            "ast2400.io", AST2400_IOMEM_SIZE);

    memory_region_add_subregion_overlap(get_system_memory(), AST2400_IOMEM_BASE,

            &s->iomem, -1);

    memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL,

            "aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE);

    memory_region_add_subregion_overlap(get_system_memory(),

                                        ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);



    /* VIC */

    object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
@@ -124,7 +135,7 @@ static void ast2400_realize(DeviceState *dev, Error **errp) 
        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, AST2400_VIC_BASE);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,

                       qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
@@ -136,7 +147,7 @@ static void ast2400_realize(DeviceState *dev, Error **errp) 
        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, AST2400_TIMER_BASE);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);

    for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {

        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
@@ -148,12 +159,12 @@ static void ast2400_realize(DeviceState *dev, Error **errp) 
        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, AST2400_SCU_BASE);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);



    /* UART - attach an 8250 to the IO space as our UART5 */

    if (serial_hds[0]) {

        qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);

        serial_mm_init(&s->iomem, AST2400_UART_5_BASE, 2,

        serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,

                       uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);

    }
@@ -163,7 +174,7 @@ static void ast2400_realize(DeviceState *dev, Error **errp) 
        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, AST2400_I2C_BASE);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,

                       qdev_get_gpio_in(DEVICE(&s->vic), 12));
@@ -175,8 +186,8 @@ static void ast2400_realize(DeviceState *dev, Error **errp) 
        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 0, AST2400_FMC_BASE);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 1, AST2400_FMC_FLASH_BASE);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 0, ASPEED_SOC_FMC_BASE);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->smc), 1, ASPEED_SOC_FMC_FLASH_BASE);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->smc), 0,

                       qdev_get_gpio_in(DEVICE(&s->vic), 19));
@@ -188,8 +199,8 @@ static void ast2400_realize(DeviceState *dev, Error **errp) 
        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, AST2400_SPI_BASE);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, AST2400_SPI_FLASH_BASE);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, ASPEED_SOC_SPI_BASE);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, ASPEED_SOC_SPI_FLASH_BASE);



    /* SDMC - SDRAM Memory Controller */

    object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
@@ -197,14 +208,16 @@ static void ast2400_realize(DeviceState *dev, Error **errp) 
        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, AST2400_SDMC_BASE);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);

}



static void ast2400_class_init(ObjectClass *oc, void *data)

static void aspeed_soc_class_init(ObjectClass *oc, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(oc);

    AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);



    dc->realize = ast2400_realize;

    sc->info = (AspeedSoCInfo *) data;

    dc->realize = aspeed_soc_realize;



    /*

     * Reason: creates an ARM CPU, thus use after free(), see
@@ -213,17 +226,29 @@ static void ast2400_class_init(ObjectClass *oc, void *data) 
    dc->cannot_destroy_with_object_finalize_yet = true;

}



static const TypeInfo ast2400_type_info = {

    .name = TYPE_AST2400,

    .parent = TYPE_SYS_BUS_DEVICE,

    .instance_size = sizeof(AST2400State),

    .instance_init = ast2400_init,

    .class_init = ast2400_class_init,

static const TypeInfo aspeed_soc_type_info = {

    .name           = TYPE_ASPEED_SOC,

    .parent         = TYPE_DEVICE,

    .instance_init  = aspeed_soc_init,

    .instance_size  = sizeof(AspeedSoCState),

    .class_size     = sizeof(AspeedSoCClass),

    .abstract       = true,

};



static void ast2400_register_types(void)

static void aspeed_soc_register_types(void)

{

    type_register_static(&ast2400_type_info);

    int i;



    type_register_static(&aspeed_soc_type_info);

    for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {

        TypeInfo ti = {

            .name       = aspeed_socs[i].name,

            .parent     = TYPE_ASPEED_SOC,

            .class_init = aspeed_soc_class_init,

            .class_data = (void *) &aspeed_socs[i],

        };

        type_register(&ti);

    }

}



type_init(ast2400_register_types)
 
type_init(aspeed_soc_register_types)

hw/arm/musicpal.c

+1 −1
Original line number Diff line number Diff line
@@ -837,7 +837,7 @@ static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, 
    s->freq = freq;



    bh = qemu_bh_new(mv88w8618_timer_tick, s);

    s->ptimer = ptimer_init(bh);

    s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);

}



static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset,