Commit e609fa71 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch... 


Merge remote-tracking branch 'remotes/edgar/tags/edgar/xilinx-next-2018-05-29-v1.for-upstream' into staging

Tag edgar/xilinx-next-2018-05-29-v1.for-upstream

# gpg: Signature made Tue 29 May 2018 09:58:30 BST
# gpg:                using RSA key 29C596780F6BCA83
# gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>"
# gpg:                 aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>"
# Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF  4151 29C5 9678 0F6B CA83

* remotes/edgar/tags/edgar/xilinx-next-2018-05-29-v1.for-upstream: (38 commits)
  target-microblaze: Consolidate MMU enabled checks
  target-microblaze: cpu_mmu_index: Fixup indentation
  target-microblaze: Use tcg_gen_movcond in eval_cond_jmp
  target-microblaze: Convert env_btarget to i64
  target-microblaze: Remove argument b in eval_cc()
  target-microblaze: Use table based condition-codes conversion
  target-microblaze: mmu: Cleanup debug log messages
  target-microblaze: Simplify address computation using tcg_gen_addi_i32()
  target-microblaze: Allow address sizes between 32 and 64 bits
  target-microblaze: Add support for extended access to TLBLO
  target-microblaze: dec_msr: Plug a temp leak
  target-microblaze: mmu: Add a configurable output address mask
  target-microblaze: mmu: Prepare for 64-bit addresses
  target-microblaze: mmu: Remove unused register state
  target-microblaze: mmu: Add R_TBLX_MISS macros
  target-microblaze: Implement MFSE EAR
  target-microblaze: Add Extended Addressing
  target-microblaze: Setup for 64bit addressing
  target-microblaze: Make special registers 64-bit
  target-microblaze: dec_msr: Fix MTS to FSR
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents dcd42560 d10367e0

configure

+1 −0
Original line number Diff line number Diff line
@@ -6844,6 +6844,7 @@ case "$target_name" in 
  microblaze|microblazeel)

    TARGET_ARCH=microblaze

    bflt="yes"

    echo "TARGET_ABI32=y" >> $config_target_mak

  ;;

  mips|mipsel)

    TARGET_ARCH=mips

linux-user/microblaze/cpu_loop.c

+2 −2
Original line number Diff line number Diff line
@@ -105,7 +105,7 @@ void cpu_loop(CPUMBState *env) 
                    queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);

                    break;

                default:

                    printf ("Unhandled hw-exception: 0x%x\n",

                    printf("Unhandled hw-exception: 0x%" PRIx64 "\n",

                           env->sregs[SR_ESR] & ESR_EC_MASK);

                    cpu_dump_state(cs, stderr, fprintf, 0);

                    exit(EXIT_FAILURE);

target/microblaze/cpu.c

+26 −4
Original line number Diff line number Diff line
@@ -72,6 +72,9 @@ static const struct { 
    {NULL, 0},

};



/* If no specific version gets selected, default to the following.  */

#define DEFAULT_CPU_VERSION "10.0"



static void mb_cpu_set_pc(CPUState *cs, vaddr value)

{

    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
@@ -125,6 +128,7 @@ static void mb_cpu_reset(CPUState *s) 
    env->mmu.c_mmu = 3;

    env->mmu.c_mmu_tlb_access = 3;

    env->mmu.c_mmu_zones = 16;

    env->mmu.c_addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);

#endif

}
@@ -141,6 +145,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 
    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);

    CPUMBState *env = &cpu->env;

    uint8_t version_code = 0;

    const char *version;

    int i = 0;

    Error *local_err = NULL;
@@ -150,6 +155,12 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 
        return;

    }



    if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {

        error_setg(errp, "addr-size %d is out of range (32 - 64)",

                   cpu->cfg.addr_size);

        return;

    }



    qemu_init_vcpu(cs);



    env->pvr.regs[0] = PVR0_USE_EXC_MASK \
@@ -162,8 +173,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 
                        | PVR2_FPU_EXC_MASK \

                        | 0;



    for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {

        if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {

    version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;

    for (i = 0; mb_cpu_lookup[i].name && version; i++) {

        if (strcmp(mb_cpu_lookup[i].name, version) == 0) {

            version_code = mb_cpu_lookup[i].version_id;

            break;

        }
@@ -195,8 +207,10 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 
    env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?

                                        PVR5_DCACHE_WRITEBACK_MASK : 0;



    env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */

    env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);

    env->pvr.regs[10] = 0x0c000000 | /* Default to spartan 3a dsp family.  */

                        (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT;

    env->pvr.regs[11] = (cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |

                        16 << 17;



    mcc->parent_realize(dev, errp);

}
@@ -226,6 +240,14 @@ static Property mb_properties[] = { 
    DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),

    DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,

                     false),

    /*

     * This is the C_ADDR_SIZE synth-time configuration option of the

     * MicroBlaze cores. Supported values range between 32 and 64.

     *

     * When set to > 32, 32bit MicroBlaze can emit load/stores

     * with extended addressing.

     */

    DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),

    /* If use-fpu > 0 - FPU is enabled

     * If use-fpu = 2 - Floating point conversion and square root instructions

     *                  are enabled

target/microblaze/cpu.h

+20 −14
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
#include "qemu-common.h"

#include "cpu-qom.h"



#define TARGET_LONG_BITS 32

#define TARGET_LONG_BITS 64



#define CPUArchState struct CPUMBState
@@ -203,6 +203,7 @@ typedef struct CPUMBState CPUMBState; 


/* Target family PVR mask */

#define PVR10_TARGET_FAMILY_MASK        0xFF000000

#define PVR10_ASIZE_SHIFT               18



/* MMU descrtiption */

#define PVR11_USE_MMU                   0xC0000000
@@ -238,19 +239,19 @@ typedef struct CPUMBState CPUMBState; 
struct CPUMBState {

    uint32_t debug;

    uint32_t btaken;

    uint32_t btarget;

    uint64_t btarget;

    uint32_t bimm;



    uint32_t imm;

    uint32_t regs[33];

    uint32_t sregs[24];

    uint32_t regs[32];

    uint64_t sregs[14];

    float_status fp_status;

    /* Stack protectors. Yes, it's a hw feature.  */

    uint32_t slr, shr;



    /* lwx/swx reserved address */

#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */

    uint32_t res_addr;

    target_ulong res_addr;

    uint32_t res_val;



    /* Internal flags.  */
@@ -277,7 +278,7 @@ struct CPUMBState { 
    /* These fields are preserved on reset.  */



    struct {

        uint32_t regs[16];

        uint32_t regs[13];

    } pvr;

};
@@ -297,6 +298,7 @@ struct MicroBlazeCPU { 
    struct {

        bool stackprot;

        uint32_t base_vectors;

        uint8_t addr_size;

        uint8_t use_fpu;

        uint8_t use_hw_mul;

        bool use_barrel;
@@ -340,8 +342,8 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo, 
/* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */

#define TARGET_PAGE_BITS 12



#define TARGET_PHYS_ADDR_SPACE_BITS 32

#define TARGET_VIRT_ADDR_SPACE_BITS 32

#define TARGET_PHYS_ADDR_SPACE_BITS 64

#define TARGET_VIRT_ADDR_SPACE_BITS 64



#define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU
@@ -358,12 +360,16 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo, 


static inline int cpu_mmu_index (CPUMBState *env, bool ifetch)

{

    MicroBlazeCPU *cpu = mb_env_get_cpu(env);



    /* Are we in nommu mode?.  */

        if (!(env->sregs[SR_MSR] & MSR_VM))

    if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) {

        return MMU_NOMMU_IDX;

    }



	if (env->sregs[SR_MSR] & MSR_UM)

    if (env->sregs[SR_MSR] & MSR_UM) {

        return MMU_USER_IDX;

    }

    return MMU_KERNEL_IDX;

}

target/microblaze/helper.c

+14 −18
Original line number Diff line number Diff line
@@ -54,22 +54,12 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, 
    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);

    CPUMBState *env = &cpu->env;

    unsigned int hit;

    unsigned int mmu_available;

    int r = 1;

    int prot;



    mmu_available = 0;

    if (cpu->cfg.use_mmu) {

        mmu_available = 1;

        if ((cpu->cfg.pvr == C_PVR_FULL) &&

            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {

            mmu_available = 0;

        }

    }



    /* Translate if the MMU is available and enabled.  */

    if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {

        target_ulong vaddr, paddr;

    if (mmu_idx != MMU_NOMMU_IDX) {

        uint32_t vaddr, paddr;

        struct microblaze_mmu_lookup lu;



        hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
@@ -152,7 +142,8 @@ void mb_cpu_do_interrupt(CPUState *cs) 
            env->sregs[SR_MSR] |= MSR_EIP;



            qemu_log_mask(CPU_LOG_INT,

                          "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",

                          "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " "

                          "esr=%" PRIx64 " iflags=%x\n",

                          env->sregs[SR_PC], env->sregs[SR_EAR],

                          env->sregs[SR_ESR], env->iflags);

            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
@@ -175,7 +166,8 @@ void mb_cpu_do_interrupt(CPUState *cs) 
                /* was the branch immprefixed?.  */

                if (env->bimm) {

                    qemu_log_mask(CPU_LOG_INT,

                                  "bimm exception at pc=%x iflags=%x\n",

                                  "bimm exception at pc=%" PRIx64 " "

                                  "iflags=%x\n",

                                  env->sregs[SR_PC], env->iflags);

                    env->regs[17] -= 4;

                    log_cpu_state_mask(CPU_LOG_INT, cs, 0);
@@ -193,7 +185,8 @@ void mb_cpu_do_interrupt(CPUState *cs) 
            env->sregs[SR_MSR] |= MSR_EIP;



            qemu_log_mask(CPU_LOG_INT,

                          "exception at pc=%x ear=%x iflags=%x\n",

                          "exception at pc=%" PRIx64 " ear=%" PRIx64 " "

                          "iflags=%x\n",

                          env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);

            log_cpu_state_mask(CPU_LOG_INT, cs, 0);

            env->iflags &= ~(IMM_FLAG | D_FLAG);
@@ -230,7 +223,8 @@ void mb_cpu_do_interrupt(CPUState *cs) 
            }

#endif

            qemu_log_mask(CPU_LOG_INT,

                         "interrupt at pc=%x msr=%x %x iflags=%x\n",

                         "interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x "

                         "iflags=%x\n",

                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);



            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
@@ -248,7 +242,8 @@ void mb_cpu_do_interrupt(CPUState *cs) 
            assert(!(env->iflags & D_FLAG));

            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;

            qemu_log_mask(CPU_LOG_INT,

                        "break at pc=%x msr=%x %x iflags=%x\n",

                        "break at pc=%" PRIx64 " msr=%" PRIx64 " %x "

                        "iflags=%x\n",

                        env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);

            log_cpu_state_mask(CPU_LOG_INT, cs, 0);

            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
@@ -274,9 +269,10 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 
    CPUMBState *env = &cpu->env;

    target_ulong vaddr, paddr = 0;

    struct microblaze_mmu_lookup lu;

    int mmu_idx = cpu_mmu_index(env, false);

    unsigned int hit;



    if (env->sregs[SR_MSR] & MSR_VM) {

    if (mmu_idx != MMU_NOMMU_IDX) {

        hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);

        if (hit) {

            vaddr = addr & TARGET_PAGE_MASK;