Commit e4e91a21 authored by Aaron Lindsay's avatar Aaron Lindsay Committed by Peter Maydell
Browse files

target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide 



This is a bug fix to ensure 64-bit reads of these registers don't read
adjacent data.

Signed-off-by: default avatarAaron Lindsay <alindsay@codeaurora.org>
Message-id: 1523997485-1905-13-git-send-email-alindsay@codeaurora.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent ac57fd24

target/arm/cpu.h

+2 −2
Original line number Diff line number Diff line
@@ -367,8 +367,8 @@ typedef struct CPUARMState { 
        uint32_t c9_data;

        uint64_t c9_pmcr; /* performance monitor control register */

        uint64_t c9_pmcnten; /* perf monitor counter enables */

        uint32_t c9_pmovsr; /* perf monitor overflow status */

        uint32_t c9_pmuserenr; /* perf monitor user enable */

        uint64_t c9_pmovsr; /* perf monitor overflow status */

        uint64_t c9_pmuserenr; /* perf monitor user enable */

        uint64_t c9_pmselr; /* perf monitor counter selection register */

        uint64_t c9_pminten; /* perf monitor interrupt enables */

        union { /* Memory attribute redirection */

target/arm/helper.c

+3 −2
Original line number Diff line number Diff line
@@ -1305,7 +1305,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { 
      .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),

      .writefn = pmcntenclr_write },

    { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,

      .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),

      .access = PL0_RW,

      .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),

      .accessfn = pmreg_access,

      .writefn = pmovsr_write,

      .raw_writefn = raw_write },
@@ -1360,7 +1361,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { 
      .accessfn = pmreg_access_xevcntr },

    { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,

      .access = PL0_R | PL1_RW, .accessfn = access_tpm,

      .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),

      .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr),

      .resetvalue = 0,

      .writefn = pmuserenr_write, .raw_writefn = raw_write },

    { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,