Commit e48929c7 authored by Qi, Yadong's avatar Qi, Yadong Committed by Michael S. Tsirkin
Browse files

intel_iommu: TM field should not be in reserved bits 



When dt is supported, TM field should not be Reserved(0).

Refer to VT-d Spec 9.8

Signed-off-by: default avatarZhang, Qi <qi1.zhang@intel.com>
Signed-off-by: default avatarQi, Yadong <yadong.qi@intel.com>
Message-Id: <20191125003321.5669-3-yadong.qi@intel.com>
Reviewed-by: default avatarPeter Xu <peterx@redhat.com>
Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>
parent ce586f3b

hw/i386/intel_iommu.c

+6 −3
Original line number Diff line number Diff line
@@ -3554,13 +3554,16 @@ static void vtd_init(IntelIOMMUState *s) 
     * Rsvd field masks for spte

     */

    vtd_spte_rsvd[0] = ~0ULL;

    vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);

    vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,

                                                  x86_iommu->dt_supported);

    vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);

    vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);

    vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);



    vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);

    vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);

    vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,

                                                         x86_iommu->dt_supported);

    vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,

                                                         x86_iommu->dt_supported);



    if (x86_iommu_ir_supported(x86_iommu)) {

        s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;

hw/i386/intel_iommu_internal.h

+10 −3
Original line number Diff line number Diff line
@@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc; 
#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8



/* Rsvd field masks for spte */

#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \

#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \

        dt_supported ? \

        (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \

        (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))

#define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \

        (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
@@ -396,9 +398,13 @@ typedef union VTDInvDesc VTDInvDesc; 
#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \

        (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))



#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \

#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \

        dt_supported ? \

        (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \

        (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))

#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \

#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \

        dt_supported ? \

        (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \

        (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))



/* Information about page-selective IOTLB invalidate */
@@ -503,5 +509,6 @@ typedef struct VTDRootEntry VTDRootEntry; 
#define VTD_SL_W                    (1ULL << 1)

#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))

#define VTD_SL_IGN_COM              0xbff0000000000000ULL

#define VTD_SL_TM                   (1ULL << 62)



#endif