Commit e46e1a74 authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: Fix broken SCTLR_EL3 reset 



The SCTLR_EL3 cpreg definition was implicitly resetting the
register state to 0, which is both wrong and clashes with
the reset done via the SCTLR definition (since sctlr[3]
is unioned with sctlr_s). This went unnoticed until recently,
when an unrelated change (commit a903c449) happened to
perturb the order of enumeration through the cpregs hashtable for
reset such that the erroneous reset happened after the correct one
rather than before it. Fix this by marking SCTLR_EL3 as an alias,
so its reset is left up to the AArch32 view.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
parent 711dc6f3

target-arm/helper.c

+1 −0
Original line number Diff line number Diff line
@@ -2752,6 +2752,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { 
      .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,

      .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },

    { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,

      .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */

      .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,

      .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,

      .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },