Commit e46b225a authored by Aurelien Jarno's avatar Aurelien Jarno Committed by Richard Henderson
Browse files

tcg/optimize: fix known-zero bits for right shift ops 



32-bit versions of sar and shr ops should not propagate known-zero bits
from the unused 32 high bits. For sar it could even lead to wrong code
being generated.

Cc: qemu-stable@nongnu.org
Reviewed-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent 7a3a0097

tcg/optimize.c

+14 −5
Original line number Diff line number Diff line
@@ -726,16 +726,25 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, 
            mask = temps[args[1]].mask & mask;

            break;



        CASE_OP_32_64(sar):

        case INDEX_op_sar_i32:

            if (temps[args[2]].state == TCG_TEMP_CONST) {

                mask = (int32_t)temps[args[1]].mask >> temps[args[2]].val;

            }

            break;

        case INDEX_op_sar_i64:

            if (temps[args[2]].state == TCG_TEMP_CONST) {

                mask = ((tcg_target_long)temps[args[1]].mask

                        >> temps[args[2]].val);

                mask = (int64_t)temps[args[1]].mask >> temps[args[2]].val;

            }

            break;



        CASE_OP_32_64(shr):

        case INDEX_op_shr_i32:

            if (temps[args[2]].state == TCG_TEMP_CONST) {

                mask = (uint32_t)temps[args[1]].mask >> temps[args[2]].val;

            }

            break;

        case INDEX_op_shr_i64:

            if (temps[args[2]].state == TCG_TEMP_CONST) {

                mask = temps[args[1]].mask >> temps[args[2]].val;

                mask = (uint64_t)temps[args[1]].mask >> temps[args[2]].val;

            }

            break;