Loading hw/dp8393x.c +6 −6 Original line number Diff line number Diff line Loading @@ -407,9 +407,9 @@ static void do_transmit_packets(dp8393xState *s) if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { /* Loopback */ s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; if (s->vc->fd_can_read(s)) { if (s->vc->can_receive(s->vc)) { s->loopback_packet = 1; s->vc->receive(s, s->tx_buffer, tx_len); s->vc->receive(s->vc, s->tx_buffer, tx_len); } } else { /* Transmit packet */ Loading Loading @@ -676,9 +676,9 @@ static CPUWriteMemoryFunc *dp8393x_write[3] = { dp8393x_writel, }; static int nic_can_receive(void *opaque) static int nic_can_receive(VLANClientState *vc) { dp8393xState *s = opaque; dp8393xState *s = vc->opaque; if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN)) return 0; Loading Loading @@ -725,10 +725,10 @@ static int receive_filter(dp8393xState *s, const uint8_t * buf, int size) return -1; } static void nic_receive(void *opaque, const uint8_t * buf, size_t size) static void nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size) { uint16_t data[10]; dp8393xState *s = opaque; dp8393xState *s = vc->opaque; int packet_type; uint32_t available, address; int width, rx_len = size; Loading hw/e1000.c +4 −4 Original line number Diff line number Diff line Loading @@ -592,17 +592,17 @@ e1000_set_link_status(VLANClientState *vc) } static int e1000_can_receive(void *opaque) e1000_can_receive(VLANClientState *vc) { E1000State *s = opaque; E1000State *s = vc->opaque; return (s->mac_reg[RCTL] & E1000_RCTL_EN); } static void e1000_receive(void *opaque, const uint8_t *buf, size_t size) e1000_receive(VLANClientState *vc, const uint8_t *buf, size_t size) { E1000State *s = opaque; E1000State *s = vc->opaque; struct e1000_rx_desc desc; target_phys_addr_t base; unsigned int n, rdt; Loading hw/eepro100.c +4 −4 Original line number Diff line number Diff line Loading @@ -1433,21 +1433,21 @@ static void pci_mmio_map(PCIDevice * pci_dev, int region_num, } } static int nic_can_receive(void *opaque) static int nic_can_receive(VLANClientState *vc) { EEPRO100State *s = opaque; EEPRO100State *s = vc->opaque; logout("%p\n", s); return get_ru_state(s) == ru_ready; //~ return !eepro100_buffer_full(s); } static void nic_receive(void *opaque, const uint8_t * buf, size_t size) static void nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size) { /* TODO: * - Magic packets should set bit 30 in power management driver register. * - Interesting packets should set bit 29 in power management driver register. */ EEPRO100State *s = opaque; EEPRO100State *s = vc->opaque; uint16_t rfd_status = 0xa000; static const uint8_t broadcast_macaddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; Loading hw/etraxfs_eth.c +3 −3 Original line number Diff line number Diff line Loading @@ -496,15 +496,15 @@ static int eth_match_groupaddr(struct fs_eth *eth, const unsigned char *sa) return match; } static int eth_can_receive(void *opaque) static int eth_can_receive(VLANClientState *vc) { return 1; } static void eth_receive(void *opaque, const uint8_t *buf, size_t size) static void eth_receive(VLANClientState *vc, const uint8_t *buf, size_t size) { unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; struct fs_eth *eth = opaque; struct fs_eth *eth = vc->opaque; int use_ma0 = eth->regs[RW_REC_CTRL] & 1; int use_ma1 = eth->regs[RW_REC_CTRL] & 2; int r_bcast = eth->regs[RW_REC_CTRL] & 8; Loading hw/mcf_fec.c +4 −4 Original line number Diff line number Diff line Loading @@ -347,15 +347,15 @@ static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value) mcf_fec_update(s); } static int mcf_fec_can_receive(void *opaque) static int mcf_fec_can_receive(VLANClientState *vc) { mcf_fec_state *s = (mcf_fec_state *)opaque; mcf_fec_state *s = vc->opaque; return s->rx_enabled; } static void mcf_fec_receive(void *opaque, const uint8_t *buf, size_t size) static void mcf_fec_receive(VLANClientState *vc, const uint8_t *buf, size_t size) { mcf_fec_state *s = (mcf_fec_state *)opaque; mcf_fec_state *s = vc->opaque; mcf_fec_bd bd; uint32_t flags = 0; uint32_t addr; Loading Loading
hw/dp8393x.c +6 −6 Original line number Diff line number Diff line Loading @@ -407,9 +407,9 @@ static void do_transmit_packets(dp8393xState *s) if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { /* Loopback */ s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; if (s->vc->fd_can_read(s)) { if (s->vc->can_receive(s->vc)) { s->loopback_packet = 1; s->vc->receive(s, s->tx_buffer, tx_len); s->vc->receive(s->vc, s->tx_buffer, tx_len); } } else { /* Transmit packet */ Loading Loading @@ -676,9 +676,9 @@ static CPUWriteMemoryFunc *dp8393x_write[3] = { dp8393x_writel, }; static int nic_can_receive(void *opaque) static int nic_can_receive(VLANClientState *vc) { dp8393xState *s = opaque; dp8393xState *s = vc->opaque; if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN)) return 0; Loading Loading @@ -725,10 +725,10 @@ static int receive_filter(dp8393xState *s, const uint8_t * buf, int size) return -1; } static void nic_receive(void *opaque, const uint8_t * buf, size_t size) static void nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size) { uint16_t data[10]; dp8393xState *s = opaque; dp8393xState *s = vc->opaque; int packet_type; uint32_t available, address; int width, rx_len = size; Loading
hw/e1000.c +4 −4 Original line number Diff line number Diff line Loading @@ -592,17 +592,17 @@ e1000_set_link_status(VLANClientState *vc) } static int e1000_can_receive(void *opaque) e1000_can_receive(VLANClientState *vc) { E1000State *s = opaque; E1000State *s = vc->opaque; return (s->mac_reg[RCTL] & E1000_RCTL_EN); } static void e1000_receive(void *opaque, const uint8_t *buf, size_t size) e1000_receive(VLANClientState *vc, const uint8_t *buf, size_t size) { E1000State *s = opaque; E1000State *s = vc->opaque; struct e1000_rx_desc desc; target_phys_addr_t base; unsigned int n, rdt; Loading
hw/eepro100.c +4 −4 Original line number Diff line number Diff line Loading @@ -1433,21 +1433,21 @@ static void pci_mmio_map(PCIDevice * pci_dev, int region_num, } } static int nic_can_receive(void *opaque) static int nic_can_receive(VLANClientState *vc) { EEPRO100State *s = opaque; EEPRO100State *s = vc->opaque; logout("%p\n", s); return get_ru_state(s) == ru_ready; //~ return !eepro100_buffer_full(s); } static void nic_receive(void *opaque, const uint8_t * buf, size_t size) static void nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size) { /* TODO: * - Magic packets should set bit 30 in power management driver register. * - Interesting packets should set bit 29 in power management driver register. */ EEPRO100State *s = opaque; EEPRO100State *s = vc->opaque; uint16_t rfd_status = 0xa000; static const uint8_t broadcast_macaddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; Loading
hw/etraxfs_eth.c +3 −3 Original line number Diff line number Diff line Loading @@ -496,15 +496,15 @@ static int eth_match_groupaddr(struct fs_eth *eth, const unsigned char *sa) return match; } static int eth_can_receive(void *opaque) static int eth_can_receive(VLANClientState *vc) { return 1; } static void eth_receive(void *opaque, const uint8_t *buf, size_t size) static void eth_receive(VLANClientState *vc, const uint8_t *buf, size_t size) { unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; struct fs_eth *eth = opaque; struct fs_eth *eth = vc->opaque; int use_ma0 = eth->regs[RW_REC_CTRL] & 1; int use_ma1 = eth->regs[RW_REC_CTRL] & 2; int r_bcast = eth->regs[RW_REC_CTRL] & 8; Loading
hw/mcf_fec.c +4 −4 Original line number Diff line number Diff line Loading @@ -347,15 +347,15 @@ static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value) mcf_fec_update(s); } static int mcf_fec_can_receive(void *opaque) static int mcf_fec_can_receive(VLANClientState *vc) { mcf_fec_state *s = (mcf_fec_state *)opaque; mcf_fec_state *s = vc->opaque; return s->rx_enabled; } static void mcf_fec_receive(void *opaque, const uint8_t *buf, size_t size) static void mcf_fec_receive(VLANClientState *vc, const uint8_t *buf, size_t size) { mcf_fec_state *s = (mcf_fec_state *)opaque; mcf_fec_state *s = vc->opaque; mcf_fec_bd bd; uint32_t flags = 0; uint32_t addr; Loading